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| description the CXD3003r is a digital signal processor lsi for cd players. this lsi incorporates a digital servo, digital filter and 1-bit dac. features all digital signal processing during playback is performed with a single chip highly integrated mounting possible due to a built- in ram digital signal processor (dsp) block playback mode supporting cav (constant angular velocity) frame jitter free 0.5 to 24 continuous playback possible with a low external clock allows relative rotational velocity readout wide capture range playback mode spindle rotational velocity following method supports 1 to 24 playback by switching the built- in vco the bit clock, which strobes the efm signal, is generated by the digital pll efm data demodulation enhanced efm frame sync signal protection refined super strategy-based powerful error correction c1: double correction, c2: quadruple correction supported during 24 playback noise reduction during track jumps auto zero-cross mute subcode demodulation and sub q data error detection digital spindle servo (built-in oversampling filter) 16-bit traverse counter asymmetry compensation circuit cpu interface on serial bus error correction monitor signal, etc. output from a new cpu interface servo auto sequencer fine search performs track jumps with high accuracy digital audio interface outputs digital level meter, peak meter bilingual compatible vco control mode digital servo (dssp) block microcomputer software-based flexible servo control offset cancel function for servo error signal auto gain control function for servo loop e:f balance, focus bias adjustment function surf jump function supporting micro two-axis digital filter and dac blocks digital de-emphasis digital attenuation 4fs oversampling filter adoption of a secondary ? noise shaper supports double-speed playback structure silicon gate cmos ic absolute maximum ratings supply voltage v dd ?.3 to +4.6 v input voltage v i ?.3 to +4.6 v (v ss ?0.3v to v dd + 0.3v) output voltage v o ?.3 to +4.6 v storage temperature tstg ?0 to +125 ? supply voltage difference v ss ?av ss ?.3 to +0.3 v v dd ?av dd ?.3 to +0.3 v recommended operating conditions supply voltage v dd * 3.0 to 4.0 v operating temperature topr ?0 to +75 ? * the v dd (min.) for the CXD3003r varies according to the playback speed and built-in vco selection. the v dd (min.) for the CXD3003r under various conditions are as shown on the following page. ?1 CXD3003r e97306a88 cd digital signal processor with built-in digital servo and dac sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 144 pin lqfp (plastic)
? 2 CXD3003r the maximum operating speed graph shows the playback speed v dd (min.) at various temperatures. the playback conditions are middle-speed vco1 and high-speed vco2 selected in cav-w mode with dspb = 1. maximum operating speed + 2 5 c + 5 5 c + 7 5 c 3 . 0 3 . 1 3 . 2 3 . 3 3 . 4 3 . 5 3 . 6 3 . 7 3 . 8 3 . 9 4 . 0 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 [ v ] [ m u l t i p l e ] ? 3 CXD3003r block diagram e r r o r c o r r e c t o r n o i s e s h a p e r p e a k d e t e c t o r o p a m p a n a s w a / d c o n v e r t e r 3 2 k r a m s e r i a l / p a r a l l e l p r o c e s s o r d i g i t a l p l l v a r i - p i t c h d o u b l e s p e e d m u x * c l v p r o c e s s o r 1 8 - t i m e s o v e r s a m p l i n g f i l t e r m i r r s e r v o i n t e r f a c e p w m g e n e r a t o r f o c u s p w m g e n e r a t o r t r a c k i n g p w m g e n e r a t o r s l e d p w m g e n e r a t o r c l o c k g e n e r a t o r s u b c o d e p t o w p r o c e s s o r t i m i n g g e n e r a t o r 1 s u b c o d e q p r o c e s s o r s e r v o a u t o s e q u e n c e r c p u i n t e r f a c e 4 f s d i g i t a l f i l t e r + 1 b i t d a c e f m d e m o d u l a t o r s y n c p r o t e c t o r p r i o r i t y e n c o d e r d / a d a t a p r o c e s s o r d i g i t a l o u t r e g i s t e r a d d r e s s g e n e r a t o r t i m i n g g e n e r a t o r 2 s e r v o d s p f o c u s s e r v o t r a c k i n g s e r v o s l e d s e r v o 8 d f c t f o k a o 1 r a o 2 f s f d r s r d r t f d r t r d r f f d r f r d r s e n s p s s l d a 0 1 t o d a 1 6 m u t e c o u t m i r r d f c t f o k d a t a c l o k x l a t d o u t m d 2 a o 1 f a o 2 r x t l o x t l i v p c o 1 x w o d a s 0 p c m d i b c k i l r c k i d t s 1 d t s 2 d a s 1 v p c o 2 x t s l d a c b l o c k s i g n a l p r o c e s s o r b l o c k s e r v o b l o c k t e s t t e s 2 t e s 3 d v d d 1 a v d d 1 a v d d 2 a v d d 3 a v d d 4 a v d d 5 d v s s 0 d v s s 1 a v s s 1 a v s s 2 a v s s 3 x r s t a d i o d v d d 0 a v s s 4 a v s s 5 4 9 t o 4 4 , 4 2 t o 3 1 , 2 9 , 2 7 m c k o v 1 6 m f s t o c 4 m c 1 6 m v c t l p d o v c o i v c o o p c o f i l i f i l o c l t v r f a c a s y i a s y o a s y e w f c k s c o r m o n f s w m d p m d s e x c k s b s o s q c k s q s o r f d c t e s e f e v c c e p w m i v c k i 1 0 1 1 0 3 1 0 4 1 0 5 1 0 6 1 1 2 1 1 3 1 1 4 1 1 5 1 1 6 1 2 0 1 2 1 1 2 2 1 2 3 1 2 4 1 2 5 1 2 8 1 2 9 1 3 0 1 3 1 1 3 2 1 3 3 1 3 4 1 3 5 1 3 6 1 3 8 1 3 9 1 4 0 1 4 1 1 4 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 6 1 7 1 8 2 0 2 1 2 2 2 3 2 6 2 8 3 0 5 1 5 2 5 5 5 6 5 7 5 9 6 0 7 0 6 9 6 7 6 3 6 4 6 5 6 6 6 1 6 2 8 2 8 3 7 5 7 7 7 8 8 7 8 6 7 9 1 0 0 9 9 9 5 9 1 9 2 o s c ? 4 CXD3003r pin configuration 3 6 3 5 3 4 3 1 3 2 3 3 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 1 4 0 3 9 3 8 3 7 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 7 0 6 9 6 8 6 7 6 3 6 4 6 5 6 6 6 1 6 2 7 1 7 2 9 7 9 6 9 5 9 4 9 1 9 2 9 3 1 0 0 9 9 9 8 1 0 1 1 0 2 1 0 3 1 0 4 1 0 5 1 0 6 1 0 7 1 0 8 7 3 7 4 8 1 8 2 8 3 8 4 7 5 7 6 7 7 7 8 8 8 8 7 8 6 8 5 7 9 8 0 8 9 9 0 1 1 1 1 0 9 1 1 0 1 1 2 1 1 3 1 1 4 1 1 5 1 1 6 1 1 7 1 1 8 1 1 9 1 2 0 1 2 1 1 2 2 1 2 3 1 2 4 1 2 5 1 2 6 1 2 7 1 2 8 1 2 9 1 3 0 1 3 1 1 3 2 1 3 3 1 3 4 1 3 5 1 3 6 1 3 7 1 3 8 1 3 9 1 4 0 1 4 1 1 4 2 1 4 3 1 4 4 f s t o n c f s t i m c k o x t s l d v s s 2 d a 0 1 d a 0 2 d a 0 4 d a 0 5 d a 0 6 d v d d 2 d a 0 7 d a 0 8 d a 0 9 d a 1 0 n c n c s q c k s q s o e x c k s b s o s c o r w f c k m u t e d o u t m d 2 d v d d 3 c 1 6 m c 4 m n c d t s 2 x r s t s c s y n c d a 0 3 n c n c d f c t m i r r c o u t d v s s 4 x l a t d a t a x w o a t s k s c l k d i r c s e n s d v d d 4 a v d d 3 a o 1 r a v s s 3 a v s s 5 x t l i x t l o a v d d 5 a v d d 4 a o 2 f a o 2 r d v s s 3 d a s 1 d a s 0 d t s 0 d t s 1 n c f o k c l o k a o 1 f n c a v s s 4 n c p w m i f s w m o n m d p m d s l o c k s s t p d v s s 5 s f d r s r d r t f d r t r d r f f d r f r d r d v d d 5 n c v c o o v c o i t e s t t e s 2 t e s 3 p d o v c k i v 1 6 m a v d d 2 i g e n a v s s 2 a d i o r f d c c e t e n c n c t e s t a n c n c n c n c s e v p c o 2 v c t l f i l o f i l i p c o c l t v a v s s 1 r f a c b i a s a s y i a s y o a v d d 1 n c d v d d 1 d v s s 1 a s y e p s s l w d c k l r c k l r c k i d a 1 6 p c m d i d a 1 5 d a 1 4 d a 1 3 d a 1 2 d a 1 1 n c n c v c v p c o 1 f e b c k i ? 5 CXD3003r pin description pin no. 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 39 40 i i i o o i o i o i i i i o i i o o i o i o i o o o o o o 1, z, 0 1, z, 0 analog 1, z, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 sled error signal input. focus error signal input. center voltage input. wide-band efm pll vco2 charge pump output. wide-band efm pll vco2 charge pump output 2. turned on and off by $e command fcsw. wide-band efm pll vco2 control voltage input. master pll filter output (slave = digital pll). master pll filter input. master pll charge pump output. multiplier vco control voltage input. analog gnd. efm signal input. asymmetry circuit constant current input. asymmetry comparator voltage input. efm full-swing output (low = v ss , high = v dd ). analog power supply. digital power supply. digital gnd. asymmetry circuit on/off (low = off, high = on). audio data output mode switching input (low: serial, high: parallel). d/a interface for 48-bit slot. word clock f = 2fs. d/a interface for 48-bit slot. lr clock f = fs. lr clock input to dac (48-bit slot). da16 (msb) output when pssl = 1, 48-bit slot serial data output (two's complement, msb first) when pssl = 0. audio data input to dac (48-bit slot). da15 output when pssl = 1, 48-bit slot bit clock output when pssl = 0. bit clock input to dac (48-bit slot). da14 output when pssl = 1, 64-bit slot serial data output (two's complement, lsb first) when pssl = 0. da13 output when pssl = 1, 64-bit slot bit clock output when pssl = 0. da12 output when pssl = 1, 64-bit slot lr clock output when pssl = 0. da11 output when pssl = 1, gtop output when pssl = 0. da10 output when pssl = 1, xugf output when pssl = 0. da09 output when pssl = 1, xplck output when pssl = 0. se fe vc vpco1 vpco2 vctl filo fili pco cltv av ss 1 rfac bias asyi asyo av dd 1 dv dd 1 dv ss 1 asye pssl wdck lrck lrcki da16 pcmdi da15 bcki da14 da13 da12 da11 da10 da09 symbol i/o description ? 6 CXD3003r 41 42 43 44 45 46 47 48 49 50 51 52 53 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 75 76 77 78 79 80 81 82 o o o o o o o o i o i o o o i o i o o o i o i i i i i i i i i o 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, z, 0 da08 output when pssl = 1, gfs output when pssl = 0. da07 output when pssl = 1, rfck output when pssl = 0. digital power supply. da06 output when pssl = 1, c2po output when pssl = 0. da05 output when pssl = 1, xraof output when pssl = 0. da04 output when pssl = 1, mnt3 output when pssl = 0. da03 output when pssl = 1, mnt2 output when pssl = 0. da02 output when pssl = 1, mnt1 output when pssl = 0. da01 output when pssl = 1, mnt0 output when pssl = 0. digital gnd. crystal selection input. clock output. inverted output of xtli. 2/3 frequency division input for xtli pin. 2/3 frequency division output for xtli pin. does not change with variable pitch. 1/4 frequency division output for xtli pin. changes with variable pitch. 16.9344mhz output. changes simultaneously with variable pitch. digital power supply. digital out on/off control (low = off, high = on). digital out output. mute (low: off, high: on). wfck (write frame clock) output. outputs a high signal when either subcode sync s0 or s1 is detected. sub p to w serial output. sbso readout clock input. sub q 80-bit and pcm peak and level data 16-bit output. sqso readout clock input. grscor re-synchronization input. normally low, re-syncronization is executed when high. system reset. reset when low. dac test pin. normally fixed to high. dac test pin. normally fixed to high. dac test pin. normally fixed to low. dac sync window open input. normally high, window open when low. dac test pin. normally fixed to high. dac test pin. normally fixed to low. digital gnd. analog gnd. channel 2 dac pwm output (reversed phase). da08 da07 dv dd 2 da06 da05 da04 da03 da02 da01 dv ss 2 xtsl mcko fsti fsto c4m c16m dv dd 3 md2 dout mute wfck scor sbso exck sqso sqck scsy xrst dts2 dts1 dts0 xwo das0 das1 dv ss 3 av ss 4 ao2r pin no. symbol i/o description ? 7 CXD3003r 83 84 85 86 87 88 89 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 111 112 113 114 115 116 117 118 119 120 121 122 o o i o o o i i i i i i i/o i/o i/o i/o i o o o o i/o i o o o 1, z, 0 1, 0 1, z, 0 1, z, 0 1, z, 0 1, 0 1, 0 1, 0 1, 0 1, z, 0 1, 0 1, z, 0 1, z, 0 1, 0 1, 0 1, 0 1, 0 channel 2 dac pwm output (forward phase). analog power supply. master clock power supply. master clock crystal oscillation circuit output. master clock crystal oscillation circuit input. master clock gnd. analog gnd. channel 1 dac pwm output (forward phase). channel 1 dac pwm output (reversed phase). analog power supply. digital power supply. sens output to cpu. used during 1-track jumps. sens serial data readout clock input. anti-shock pin. serial data input from cpu. latch input from cpu. serial data is latched at the falling edge. serial data transfer clock input from cpu. digital gnd. track count signal i/o. mirror signal i/o. defect signal i/o. focus ok signal i/o. test pin. leave this open. spindle motor external pin input. spindle motor output filter switching output. grscor output when $8 command scor sel = high. spindle motor on/off control output. spindle motor servo control output. spindle motor servo control output. gfs is sampled at 460hz; when gfs is high, this pin outputs a high signal. if gfs is low eight consecutive samples, this pin outputs low. input when lkin = high. disc innermost track detection signal input. digital gnd. sled drive output. sled drive output. tracking drive output. ao2f av dd 4 av dd 5 xtlo xtli av ss 5 av ss 3 ao1f ao1r av dd 3 av dd 4 sens dirc sclk atsk data xlat clok dv ss 4 cout mirr dfct fok testa pwmi fsw mon mdp mds lock sstp dv ss 5 sfdr srdr tfdr pin no. symbol i/o description ? 8 CXD3003r * in the CXD3003r, the following pins are nc. pins 1, 2, 19, 35, 36, 37, 38, 54, 71, 72, 73, 74, 90, 107, 108, 109, 110, 127, 143 and 144 notes) the 64-bit slot is an lsb first, two's complement output. the 48-bit slot is an msb first, two's complement output. gtop is used to monitor the frame sync protection status. (high: sync protection window released.) xugf is the frame sync obtained from the efm signal, and is negative pulse. it is the signal before sync protection. xplck is the inverse of the efm pll clock. the pll is designed so that the falling edge and the efm signal transition point coincide. the gfs signal goes high when the frame sync and the insertion protection timing match. rfck is derived from the crystal accuracy, and has a cycle of 136 s. c2po represents the data error status. xraof is generated when the 32k ram exceeds the 28f jitter margin. 123 124 125 126 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 o o o o i i i i o i o i o i i i 1, 0 1, 0 1, 0 1, 0 1, z, 0 1, z, 0 tracking drive output. focus drive output. focus drive output. digital power supply. analog efm pll oscillation circuit output. analog efm pll oscillation circuit input. flock = 8.6436mhz test pin. normally fixed to low. test pin. normally fixed to low. test pin. normally fixed to low. analog efm pll charge pump output. variable pitch clock input from the external vco. fcenter = 16.9344mhz set vcki to low when the external clock is not input to this pin. wide-band efm pll vco2 oscillation output. analog power supply. connects the operational amplifier current source reference resistance connection. analog gnd. operational amplifier output. rf signal input. center servo analog input. tracking error signal input. trdr ffdr frdr dv dd 5 vcoo vcoi test tes2 tes3 pdo vcki v16m av dd 2 igen av ss 2 adio rfdc ce te pin no. symbol i/o description ? 9 CXD3003r electrical characteristics 1. dc characteristics (v dd = av dd = 3.3v 10%, v ss = av ss = 0v, topr = ?0 to +75 c) item input leak current (1) input leak current (2) tri-state pin output leak current high level input voltage low level input voltage high level input voltage low level input voltage high level input voltage low level input voltage high level input voltage low level input voltage input voltage input voltage high level output voltage low level output voltage high level output voltage low level output voltage high level output voltage low level output voltage low level output voltage high level output voltage low level output voltage input voltage (1) input voltage (2) input voltage (3) input voltage (4) input voltage (5) input voltage (6) output voltage (1) output voltage (2) output voltage (3) output voltage (4) output voltage (5) v ih (1) v il (1) v ih (2) v il (2) v ih (3) v il (3) v ih (4) v il (4) v in (5) v in (6) v oh (1) v ol (1) v oh (2) v ol (2) v oh (3) v ol (3) v ol (4) v oh (5) v ol (5) i li (1) i li (2) i lo 0.7v dd 0.7v dd 0.7v dd 0.7v dd v ss v ss v dd ?0.4 0 v dd ?0.4 0 v dd ?0.2 0 0 v dd ?0.5 0 ?0 ?0 ? 0.2v dd 0.2v dd 0.2v dd 0.2v dd v dd v dd v dd 0.4 v dd 0.4 v dd 0.4 0.4 v dd 0.4 10 20 5 v v v v v v v v v v v v v v v v v v v a a a conditions min. typ. max. unit applicable pins applicable pins * 1 bcki, dts0, dts1, dts2, lrcki, pcmdi, tes2, tes3, test * 2 asye, fsti, vcki * 3 atsk, data, dirc, md2, pwmi, sstp, xlat, xtsl, xwo * 4 clok, exck, mute, sclk, scsy, sqck, xrst * 5 asyi, bias, cltv, fili, igen, rfac, vctl * 6 ce, fe, se, te, vc, rfdc * 7 asyo, c16m, c4m, da01 to da16, das0, das1, dout, ffdr, frdr, fsto, lrck, mon, pssl, sbso, scor, sfdr, sqso, srdr, tfdr, trdr, wdck, wfck * 8 fsw * 9 mcko * 10 ao1f, ao1r, ao2f, ao2r, mdp, mds, pco, pdo, sens, v16m, vpco1, vpco2 * 11 filo * 12 cout, dfct, fok, lock, mirr schmitt input v i 5.5v v i 5.5v schmitt input analog input analog input i oh = ?ma i ol = 8ma i oh = ?ma i ol = 4ma i oh = ?ma i ol = 4ma i ol = 4ma i oh = ?.28ma i oh = 0.36ma v i = 0 to 5.5v v i = 0.25v dd to 0.75v dd v o = 0 to 3.6v * 1 , * 12 * 2 * 3 * 4 * 5 * 6 * 9 * 7 , * 10 * 12 * 7 , * 10 * 12 * 8 * 11 * 3 , * 4 , * 5 * 6 * 10 2. ac characteristics (1) xtli pin, vcoi pin (a) when using self-excited oscillation (topr = ?0 to +75 c, v dd = av dd = 3.3v 10%) (b) when inputting pulses to xtli and vcoi pins (topr = ?0 to +75 c, v dd = av dd = 3.3v 10%) (c) when inputting sine waves to xtli and vcoi pins via a capacitor (topr = ?0 to +75 c, v dd = av dd = 3.3v 10%) ? 10 CXD3003r oscillation frequency f max 7 34 mhz item symbol min. typ. max. unit high level pulse width t whx 13 500 ns low level pulse width t wlx 13 500 ns pulse cycle t cx 26 1000 ns input high level v ihx v dd ?1.0 v input low level v ilx 0.8 v rise time, fall time t r , t f 10 ns item symbol min. typ. max. unit input amplitude v i 2.0 v dd + 0.3 vp-p item symbol min. typ. max. unit t r t f t w h x t w l x t c x v i l x v i h x 0 . 1 v i h x 0 . 9 v i h x x t l i v d d / 2 ? 11 CXD3003r (2) clok, data, xlat, sqck and exck pins (v dd = av dd = 3.3v 10%, v ss = av ss = 0v, topr = ?0 to +75 c) clock frequency clock pulse width setup time hold time delay time latch pulse width exck sqck frequency exck sqck pulse width cnin frequency * cnin pulse width * f ck t wck t su t h t d t wl f t t wt f t t wt 30 30 30 30 750 750 7.5 16 0.65 65 mhz ns ns ns ns ns mhz ns khz s item symbol min. typ. max. unit t w c k t w c k 1 / f c k t h t s u t w l t d 1 / f t t w t t w t t h t s u c l o k d a t a x l a t e x c k s q c k c n i n s b s o s q s o * only when $44 and $45 are executed. ? 12 CXD3003r (4) cout, mirr and dfct pins operating frequency (v dd = av dd = 3.3v 10%, v ss = av ss = 0v, topr = ?0 to +75 c) cout maximum operating frequency mirr maximum operating frequency dfct maximum operating frequency f cout f mirr f dfcth 40 40 5 khz khz khz * 1 * 2 * 3 item symbol min. typ. max. unit conditions * 1 when using a high-speed traverse tzc. * 2 when the rf signal continuously satisfies the following conditions during the above traverse. a = 0.11v dd to 0.23v dd 25% * 3 during complete rf signal omission. when settings related to dfct signal generation are typ. (3) sclk pin sclk frequency sclk pulse width delay time f sclk t spw t dls 31.3 15 16 mhz ns s item symbol min. typ. max. unit t s p w t d l s 1 / f s c l k m s b l s b x l a t s c l k s e r i a l r e a d o u t d a t a ( s e n s ) a b b a + b ? 13 CXD3003r (5) bcki, lrcki and pcmdi pins (v dd = 3.3v 10%, topr = ?0 to +75 c) input bcki frequency input bcki pulse width input data setup time input data hold time input lrck setup time input lrck hold time t bck t wib t ids t idh t ilrh t ilrs 100 10 15 10 15 4.5 mhz ns item symbol min. typ. max. unit t i l r h t w i b t w i b t i d h t i d s t i l r s 5 0 % b c k i p c m d i l r c k i ? 14 CXD3003r dac analog characteristics measurement conditions (ta = 25 c, v dd = 3.3v, fs = 44.1khz, signal frequency = 1khz, measurement band = 4hz to 20khz, master clock = 768fs) s/n ratio thd + n dynamic range channel separation output level difference in gain between channels 93 0.015 91 91 1.7 0.1 db % db db v (rms) db item typ. unit (eiaj) * 1 (eiaj) (eiaj) * 1 , * 2 (eiaj) remarks c x d 3 0 0 3 r a o 1 f a o 1 r 3 . 9 k 1 3 0 k 3 . 9 k 3 . 9 k 1 3 0 k 3 . 9 k 4 7 p 4 7 p 4 . 7 k 4 . 7 k 4 . 7 k 8 2 0 p 4 . 7 k 8 2 0 p 4 . 7 k 4 . 7 k 0 . 0 1 5 4 . 7 k 1 8 0 0 p 8 2 p 1 2 k 1 0 0 2 2 o u t p u t * 1 using "a" weighting filter * 2 ?0 db, 1khz input the analog characteristics measurement circuit is shown below. a o 1 r a o 2 f a o 2 r a o 1 f t e s t d i s k d a t a a u d i o c i r c u i t a n a l o g 1 c h 2 c h a u d i o a n a l y z e r s h i b a s o k u ( a m 5 1 a ) 7 6 8 f s c x d 3 0 0 3 r block diagram of analog characteristics measurement ? 15 CXD3003r contents [1] cpu interface ?-1. cpu interface timing ........................................................................................................................ 16 ?-2. cpu interface command table ........................................................................................................ 16 ?-3. cpu command presets .................................................................................................................... 26 ?-4. description of sens signals ............................................................................................................. 31 [2] subcode interface ?-1. p to w subcode readout .................................................................................................................. 65 ?-2. 80-bit sub q readout ........................................................................................................................ 65 [3] description of modes ?-1. clv-n mode ............................................................................................................................... ....... 71 ?-2. clv-w mode ............................................................................................................................... ...... 71 ?-3. cav-w mode ............................................................................................................................... ...... 71 ?-4. vco-c mode ............................................................................................................................... ...... 72 [4] description of other functions ?-1. channel clock regeneration by the digital pll circuit .................................................................... 74 ?-2. frame sync protection ...................................................................................................................... 76 ?-3. error correction ............................................................................................................................... .. 76 ?-4. da interface ............................................................................................................................... ........ 77 ?-5. digital out ............................................................................................................................... ........... 80 ?-6. servo auto sequence ....................................................................................................................... 81 ?-7. digital clv ............................................................................................................................... .......... 89 ?-8. playback speed ............................................................................................................................... . 90 ?-9. dac block playback speed .............................................................................................................. 91 ?-10. dac block input timing .................................................................................................................... 91 ?-11. asymmetry compensation ................................................................................................................ 92 ?-12. CXD3003 clock system .................................................................................................................... 93 [5] description of servo signal processing system functions and commands ?-1. general description of the servo signal processing system ............................................................ 94 ?-2. digital servo block master clock (mck) ........................................................................................... 95 ?-3. avrg measurement and compensation .......................................................................................... 95 ?-4. e:f balance adjustment function ..................................................................................................... 97 ?-5. fcs bias adjustment function .......................................................................................................... 97 ?-6. agcntl function ............................................................................................................................. 99 ?-7. fcs servo and fcs search ........................................................................................................... 101 ?-8. trk and sld servo control ........................................................................................................... 102 ?-9. mirr and dfct signal generation ................................................................................................ 103 ?-10. dfct countermeasure circuit ........................................................................................................ 104 ?-11. anti-shock circuit ............................................................................................................................ 104 ?-12. brake circuit ............................................................................................................................... ..... 105 ?-13. cout signal ............................................................................................................................... .... 106 ?-14. serial readout circuit ...................................................................................................................... 106 ?-15. writing to the coefficient ram ........................................................................................................ 107 ?-16. pwm output ............................................................................................................................... ..... 107 ?-17. dirc input pin ............................................................................................................................... .. 109 ?-18. servo status changes produced by the lock signal ................................................................... 110 ?-19. description of commands and data sets ....................................................................................... 110 ?-20. list of servo filter coefficients ........................................................................................................ 125 ?-21. filter composition ............................................................................................................................ 127 ?-22. tracking and focus frequency response .............................................................................. 134 [6] application circuit ............................................................................................................................... ... 135 explanation of abbreviations avrg: average agcntl: auto gain control fcs: focus trk: tracking sld: sled dfct: defect ? 16 CXD3003r [1] cpu interface ?-1. cpu interface timing cpu interface this interface uses data, clok and xlat to set the modes. the interface timing chart is shown below. the internal registers are initialized by a reset when xrst = 0. ?-2. cpu interface command table total bit length for each register register 0 to 2 3 4 to 6 7 8 9 a b c d e 8 bits 8 to 24 bits 16 bits 20 bits 24 bits 20 bits 28 bits 20 bits 16 bits 20 bits 20 bits total bit length 3 0 n s o r m o r e d 1 8 d 1 9 d 2 0 d 2 1 d 2 2 d 2 3 7 5 0 n s o r m o r e v a l i d c l o k d a t a x l a t r e g i s t e r s d 0 d 1 ? 17 CXD3003r focus servo on (focus gain normal) focus servo on (focus gain down) focus servo off, 0v out focus servo off, focus search voltage out focus search voltage down focus seach voltage up anti shock on anti shock off brake on brake off tracking gain normal tracking gain up tracking gain up filter select 1 tracking gain up filter select 2 1 1 0 0 0 0 1 0 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0 1 focus control tracking control register command address d23 to d20 data 1 d19 d18 d17 d16 data 2 d15 d14 d13 d12 data 3 d11 d10 d9 d8 data 4 d7 d6 d5 d4 data 5 d3 d2 d1 d0 command table ($0x to 1x) ? don? care ? 18 CXD3003r tracking servo off tracking servo on forward track jump reverse track jump sled servo off sled servo on forward sled move reverse sled move sled kick level ( 1 basic value) (default) sled kick level ( 2 basic value) sled kick level ( 3 basic value) sled kick level ( 4 basic value) 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 2 3 0 0 1 0 0 0 1 1 tracking mode select register command address d23 to d20 register command address d23 to d20 data 1 d19 d18 d17 d16 data 1 d19 d18 d17 d16 data 2 d15 d14 d13 d12 data 2 d15 d14 d13 d12 data 3 d11 d10 d9 d8 data 4 d7 d6 d5 d4 data 5 d3 d2 d1 d0 data 3 d11 d10 d9 d8 data 4 d7 d6 d5 d4 data 5 d3 d2 d1 d0 ? don? care command table ($2x to 3x) ? 19 CXD3003r kram data (k00) sled input gain kram data (k01) sled low boost filter a-h kram data (k02) sled low boost filter a-l kram data (k03) sled low boost filter b-h kram data (k04) sled low boost filter b-l kram data (k05) sled output gain kram data (k06) focus input gain kram data (k07) sled auto gain kram data (k08) focus high cut filter a kram data (k09) focus high cut filter b kram data (k0a) focus low boost filter a-h kram data (k0b) focus low boost filter a-l kram data (k0c) focus low boost filter b-h kram data (k0d) focus low boost filter b-l kram data (k0e) focus phase compensate filter a kram data (k0f) focus defect hold gain 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 3 0 0 1 1 0 1 0 0 0 0 0 0 select register command address 1 d23 to d20 address 2 d19 to d16 address 3 d15 to d12 address 4 d11 d10 d9 d8 data 1 d7 d6 d5 d4 data 2 d3 d2 d1 d0 command table ($340x) ? 20 CXD3003r kram data (k10) focus phase compensate filter b kram data (k11) focus output gain kram data (k12) anti shock input gain kram data (k13) focus auto gain kram data (k14) hptzc / auto gain high pass filter a kram data (k15) hptzc / auto gain high pass filter b kram data (k16) anti shock high pass filter a kram data (k17) hptzc / auto gain low pass filter b kram data (k18) fix kram data (k19) tracking input gain kram data (k1a) tracking high cut filter a kram data (k1b) tracking high cut filter b kram data (k1c) tracking low boost filter a-h kram data (k1d) tracking low boost filter a-l kram data (k1e) tracking low boost filter b-h kram data (k1f) tracking low boost filter b-l 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 3 0 0 1 1 0 1 0 0 0 0 0 1 select register command address 1 d23 to d20 address 2 d19 to d16 address 3 d15 to d12 address 4 d11 d10 d9 d8 data 1 d7 d6 d5 d4 data 2 d3 d2 d1 d0 command table ($341x) ? 21 CXD3003r kram data (k20) tracking phase compensate filter a kram data (k21) tracking phase compensate filter b kram data (k22) tracking output gain kram data (k23) tracking auto gain kram data (k24) focus gain down high cut filter a kram data (k25) focus gain down high cut filter b kram data (k26) focus gain down low boost filter a-h kram data (k27) focus gain down low boost filter a-l kram data (k28) focus gain down low boost filter b-h kram data (k29) focus gain down low boost filter b-l kram data (k2a) focus gain down phase compensate filter a kram data (k2b) focus gain down defect hold gain kram data (k2c) focus gain down phase compensate filter b kram data (k2d) focus gain down output gain kram data (k2e) not used kram data (k2f) not used 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 3 0 0 1 1 0 1 0 0 0 0 1 0 select register command address 1 d23 to d20 address 2 d19 to d16 address 3 d15 to d12 address 4 d11 d10 d9 d8 data 1 d7 d6 d5 d4 data 2 d3 d2 d1 d0 command table ($342x) ? 22 CXD3003r kram data (k30) fix kram data (k31) anti shock low pass filter b kram data (k32) not used kram data (k33) anti shock high pass filter b-h kram data (k34) anti shock high pass filter b-l kram data (k35) anti shock filter comparate gain kram data (k36) tracking gain up2 high cut filter a kram data (k37) tracking gain up2 high cut filter b kram data (k38) tracking gain up2 low boost filter a-h kram data (k39) tracking gain up2 low boost filter a-l kram data (k3a) tracking gain up2 low boost filter b-h kram data (k3b) tracking gain up2 low boost filter b-l kram data (k3c) tracking gain up phase compensate filter a kram data (k3d) tracking gain up phase compensate filter b kram data (k3e) tracking gain up output gain kram data (k3f) not used 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 3 0 0 1 1 0 1 0 0 0 0 1 1 select register command address 1 d23 to d20 address 2 d19 to d16 address 3 d15 to d12 address 4 d11 d10 d9 d8 data 1 d7 d6 d5 d4 data 2 d3 d2 d1 d0 command table ($343x) ? 23 CXD3003r kram data (k40) tracking hold filter input gain kram data (k41) tracking hold filter a-h kram data (k42) tracking hold filter a-l kram data (k43) tracking hold filter b-h kram data (k44) tracking hold filter b-l kram data (k45) tracking hold filter output gain kram data (k46) not used kram data (k47) not used kram data (k48) focus hold filter input gain kram data (k49) focus hold filter a-h kram data (k4a) focus hold filter a-l kram data (k4b) focus hold filter b-h kram data (k4c) focus hold filter b-l kram data (k4d) focus hold filter output gain kram data (k4e) not used kram data (k4f) not used 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 3 0 0 1 1 0 1 0 0 0 1 0 0 select register command address 1 d23 to d20 address 2 d19 to d16 address 3 d15 to d12 address 4 d11 d10 d9 d8 data 1 d7 d6 d5 d4 data 2 d3 d2 d1 d0 command table ($344x) ? 24 CXD3003r 0 0 1 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 focus bias limit focus bias data trvsc data focus search speed/ voltage/auto gain dtzc/track jump voltage/auto gain fzsl/sled move/ voltage/auto gain level/auto gain/ dfsw/ (initialize) serial data read mode/select focus bias operation for mirr/ dfct/fok tzc/cout bottom/mirr sled filter filter others 3 0 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 fbl9 fb9 tv9 fbl8 fb8 tv8 fbl7 fb7 tv7 fbl6 fb6 tv6 fbl5 fb5 tv5 fbl4 fb4 tv4 fbl3 fb3 tv3 fbl2 fb2 tv2 fbl1 fb1 tv1 tv0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 ft1 tdzc fzsh vclm dac 0 sfo2 ft0 dtzc fzsl vclc sd6 fbon sfo1 fs5 tj5 sm5 flm sd5 fbss sdf2 fs4 tj4 sm4 flc0 sd4 fbup sdf1 fs3 tj3 sm3 rflm sd3 fbv1 max2 fs2 tj2 sm2 rflc sd2 fbv0 max1 fs1 tj1 sm1 agf sd1 0 sfox fs0 tj0 sm0 agt sd0 tjd0 btf ftz sfjp ags dfsw 0 fps1 d2v2 fg6 tg6 agj lksw 0 fps0 d2v1 fg5 tg5 aggf tblm 0 tps1 d1v2 fg4 tg4 aggt tclm 0 tps0 d1v1 fg3 tg3 agv1 flc1 0 0 rint fg2 tg2 agv2 tlc2 0 sjhd 0 fg1 tg1 aghs tlc1 0 inbk 0 fg0 tg0 aght tlc0 0 mti0 0 1 1 1 1 1 1 1 1 0 1 f1nm 0 f1dm agg4 f3nm xt4d f3dm xt2d t1nm 0 t1um drr2 t3nm drr1 t3um drr0 dfis 0 tlcd asfg 0 ftq lkin lpas coin sro1 mdfi sro0 miri aghf xt1d 0 1 1 0 0 0 1 coss sfid cots sfsk cetz thid cetf thsk cot2 0 cot1 tld2 mot2 tld1 0 tld0 bts1 0 bts0 0 mrc1 0 mrc0 0 0 0 0 0 0 0 0 0 select register command address 1 d23 to d20 d19 d18 d17 d16 address 2 d15 d14 d13 d12 data 1 d11 d10 d9 d8 data 2 d7 d6 d5 d4 data 3 d3 d2 d1 d0 address d23 to d20 d19 d18 d17 d16 data 1 d15 d14 d13 d12 data 2 d11 d10 d9 d8 data 3 d7 d6 d5 d4 data 4 d3 d2 d1 d0 command table ($34fx to 3fx) ? don? care ? 25 CXD3003r auto sequence blind (a, e), brake (b), overflow (c, g) sled kick, brake (d), kick (f) auto sequence (n) track jump count setting mode specification function specification audio ctrl traverse monitor counter setting spindle servo coefficient setting clv ctrl spd mode 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 as3 tr3 sd3 32768 cd- rom dclv on/off 0 32768 gain mdp1 dclv pwm md cm3 as2 tr2 sd2 16384 dout mute dspb on/off 0 16384 gain mdp0 tb cm2 as1 tr1 sd1 8192 dout mute-f aseq on/off mute 8192 gain mds1 tp cm1 as0 tr0 sd0 4096 wsel dpll on/off att 4096 gain mds0 clvs gain cm0 mt3 0 kf3 2048 vco sel biligl main pct1 2048 gain dclv1 vp7 epwm mt2 0 kf2 1024 ashs biligl sub pct2 1024 gain dclv0 vp6 spdc mt1 0 kf1 512 soct flfc dads 512 pcc1 vp5 icap mt0 0 kf0 256 vco sel2 xwoc soc2 256 pcc0 vp4 sfsl lssl 0 0 128 ksl3 dac emp at1d7 128 0 vp3 vc2c 0 0 0 64 ksl2 dac att at1d6 64 0 vp2 hifc 0 0 0 32 ksl1 0 at1d5 32 0 vp1 lpwr 0 0 0 16 ksl0 0 at1d4 16 0 vp0 vpon 8 vc01 cs1 plm3 at1d3 8 vp ctl1 gain cav1 4 vco1 cs0 plm2 at1d2 4 vp ctl0 gain cav0 2 xvco2 thru plm1 at1d1 2 0 fcsw 1 vco2 cs plm0 at1d0 1 0 inv vpco 4 5 6 7 8 9 a b c d e register command address d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 data 1 data 2 data 3 data 4 command table ($4x to ex) ? don? care mode specification 1 0 0 0 erc4 scor sel scsy 0 8 audio ctrl 1 0 1 0 at2d7 at2d6 at2d5 at2d4 at2d3 at2d2 at2d1 at2d0 a register command address data 1 data 2 data 3 data 4 d7 d6 d5 d4 d3 d2 d1 d0 data 5 data 6 ? 26 CXD3003r focus servo off, 0v out tracking gain up filter select 1 tracking servo off sled servo off sled kick level ( 1 basic value) (default) kram data ($3400xx to $344fxx) 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 0 0 0 0 0 0 1 0 0 1 0 focus control tracking control tracking mode register command address d23 to d20 data 1 d19 d18 d17 d16 data 2 d15 d14 d13 d12 data 3 d11 d10 d9 d8 data 4 d7 d6 d5 d4 data 5 d3 d2 d1 d0 register command 3 select address d23 to d20 0 0 1 1 0 0 1 1 0 1 0 0 0 see "coefficient rom preset values table". 0 0 0 0 data 1 d19 d18 d17 d16 data 2 d15 d14 d13 d12 data 3 d11 d10 d9 d8 data 4 d7 d6 d5 d4 data 5 d3 d2 d0 d0 address 1 d23 to d20 d19 d18 d17 d16 address 2 d15 d14 d13 d12 address 3 d11 d10 d9 d8 data 1 d7 d6 d5 d4 data 2 d3 d2 d0 d0 ?-3. cpu command presets command preset table ($0x to 34x) ? don? care ? 27 CXD3003r 0 0 1 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 focus bias limit focus bias data trvsc data focus search speed/ voltage auto gain dtzc/track jump voltage auto gain fzsl/sled move/ voltage/auto gain level/auto gain/ dfsw/ (initialize) serial data read mode/select focus bias operation for mirr/ dfct/fok tzc/cout bottom/mirr sled filter 3 0 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 filter others 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 select register command address 1 d23 to d20 d19 d18 d17 d16 address 2 d15 d14 d13 d12 data 1 d11 d10 d9 d8 data 2 d7 d6 d5 d4 data 3 d3 d2 d1 d0 address d23 to d20 d19 d18 d17 d16 data 1 d15 d14 d13 d12 data 2 d11 d10 d9 d8 data 3 d7 d6 d5 d4 data 4 d3 d2 d1 d0 command preset table ($34fx to 3fx) ? don? care ? 28 CXD3003r auto sequence blind (a, e), brake (b), overflow (c, g) sled kick, brake (d), kick (f) auto sequence (n) track jump count setting mode specification function specification audio ctrl traverse monitor counter setting spindle servo coefficient setting clv ctrl spd mode 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 4 5 6 7 8 9 a b c d e register command address d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 data 1 data 2 data 3 data 4 command preset table ($4x to ex) ? don? care mode specification 1 0 0 0 0 0 0 0 8 audio ctrl 1 0 1 0 1 1 1 1 1 1 1 1 a register command address data 1 data 2 data 3 data 4 d7 d6 d5 d4 d3 d2 d1 d0 data 5 data 6 ? 29 CXD3003r ? 30 CXD3003r ? 31 CXD3003r ?-4. description of sens signals sens output microcomputer serial register (latching not required) $0x $1x $2x $38 $38 $30 to 37 $3a $3b to 3f $3904 $3908 $390c $391c $391d $391f $4x $5x $6x $ax $bx $cx $ex $7x, 8x, 9x, dx, fx z z z z z z z z z z z z z z z z z gfs comp cout ov64 z fzc as tzc agok * xavebsy * sstp fbias count stop sstp te avrg reg. fe avrg reg. vc avrg reg. trvsc reg. fb reg. rfdc avrg reg. xbusy fok servo sens gfs comp cout ov64 0 9 bit 9 bit 9 bit 9 bit 9 bit 8 bit aseq = 0 aseq = 1 output data length * $38 outputs agok during agt and agf command settings, and xavebsy during avrg measurement. sstp is output in all other cases. ? 32 CXD3003r description of sens signals the sens pin is high impedance. low while the auto sequencer is in operation, high when operation terminates. outputs the same signal as the fok pin. high for "focus ok". high when the regenerated frame sync is obtained with the correct timing. counts the number of tracks set with reg.b. high when reg.b is latched, low when the initial reg.b number is input by cnin. counts the number of tracks set with reg.b. high when reg.b is latched, toggles each time the reg.b number is input by cnin. while $44 and $45 are being executed, toggles with each cnin 8-count instead of the reg.b number. low when the efm signal is lengthened by 64 channel clock pulses or more after passing through the sync detection filter. z xbusy fok gfs comp cout ov64 sens output ? 33 CXD3003r the meaning of the data for each address is explained below. $4x commands register name 4 data 1 command data 2 max timer value data 3 timer range as3 as2 as1 as0 mt3 mt2 mt1 mt0 lssl 0 0 0 command cancel fine search focus-on 1-track jump 10-track jump 2n-track jump m track move 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 rxf 1 rxf rxf rxf rxf as3 as2 as1 as0 rxf = 0 forward rxf = 1 reverse when the focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted. when the track jump commands ($44 to $45, $48 to $4d) are canceled, $25 is sent and the auto sequence is interrupted. to disable the max timer, set the max timer value to 0. $5x commands max timer value mt3 23.2ms 1.49s 11.6ms 0.74s 5.8ms 0.37s 2.9ms 0.18s 0 1 0 0 0 0 0 0 mt2 mt1 mt0 lssl 0 0 0 timer range timer tr3 tr2 tr1 tr0 blind (a, e), overflow (c, g) brake (b) 0.18ms 0.36ms 0.09ms 0.18ms 0.045ms 0.09ms 0.022ms 0.045ms ? 34 CXD3003r command data 1 data 2 data 3 data 4 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 auto sequence track jump count setting this command is used to set n when a 2n-track jump is executed, to set m when an m-track move is executed and to set the jump count when fine search is executed for auto sequence. the maximum track count is 65,535, but note that with a 2n-track jump the maximum track jump count depends on the mechanical limitations of the optical system. when the track jump count is from 0 to 15, the cout signal counted for 2n-track jumps and m-track moves; when the count is 16 or over, the mirr signal is counted. for fine search, the cout signal is counted. $7x commands auto sequence track jump count setting $6x commands register name 6 data 1 kick (d) data 2 kick (f) sd3 sd2 sd1 sd0 kf3 kf2 kf1 kf0 timer sd3 sd2 sd1 sd0 when executing kick (d) $44 or $45 when executing kick (d) $4c or $4d 23.2ms 11.6ms 11.6ms 5.8ms 5.8ms 2.9ms 2.9ms 1.45ms timer kf3 kf2 kf1 kf0 kick (f) 0.72ms 0.36ms 0.18ms 0.09ms ? 35 CXD3003r * see mute conditions (1), (2), and (4) to (6) under $ax commands for other mute conditions. md2 other mute conditions * dout mute d.out mute f dout output off 0db ? db 0db ? db 0db 0db ? db da output for 48-bit slot da output for 64-bit slot 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 command data 1 mode specification cd- rom dout mute dout mute-f wsel d23 d22 d21 d20 data 2 vco sel1 ashs soct vco sel2 d19 d18 d17 d16 $8x commands command bit dout mute = 1 dout mute = 0 when digital out is on (md2 pin = 1), dout output is muted. when digital out is on, dout output is not muted. processing command bit d. out mute f = 1 d. out mute f = 0 when digital out is on (md2 pin = 1), da output is muted. da output mute is not affected when digital out is either on or off. processing command bit cdrom = 1 cdrom = 0 c2po timing 1-3 1-3 cdrom mode; average value interpolation and pre-value hold are not performed. audio mode; average value interpolation and pre-value hold are performed. processing ? db 0db ? db 0db ? db ? 36 CXD3003r command bit sync protection window width wsel = 1 wsel = 0 26 channel clock 6 channel clock anti-rolling is enhanced. sync window protection is enhanced. application * in normal-speed playback, channel clock = 4.3218mhz. command bit function ashs = 0 ashs = 1 the command transfer rate to ssp is set to normal speed. the command transfer rate to ssp is set to half speed. command bit function soct = 0 soct = 1 sub q is output from the sqso pin. each output signal is output from the sqso pin. input the readout clock to sqck. (see timing chart 2-4.) * see "?-8. playback speed" for settings. ? 37 CXD3003r command bit processing vcosel1 = 0 vcosel1 = 1 multiplier pll vco1 is set to normal speed. multiplier pll vco1 is set to approximately twice the normal speed. command bit ksl3 ksl2 processing output of multiplier pll vco1 selected by vco1 cs1 and cs0 is 1/1 frequency-divided. output of multiplier pll vco1 selected by vco1 cs1 and cs0 is 1/2 frequency-divided. output of multiplier pll vco1 selected by vco1 cs1 and cs0 is 1/4 frequency-divided. output of multiplier pll vco1 selected by vco1 cs1 and cs0 is 1/8 frequency-divided. 0 0 1 1 0 1 0 1 * this setting is valid only when the low-speed vco is selected by vco1 cs1 and cs0. see the previous page. command data 2 mode specification vco sel1 ashs soct vco sel2 d19 d18 d17 d16 data 3 ksl3 ksl2 ksl1 ksl0 d15 d14 d13 d12 command bit processing vcosel2 = 0 vcosel2 = 1 wide-band pll vco2 is set to normal speed. wide-band pll vco2 is set to approximately twice the normal speed. command bit ksl1 ksl0 processing output of wide-band pll vco2 selected by vco2 cs is 1/1 frequency-divided. output of wide-band pll vco2 selected by vco2 cs is 1/2 frequency-divided. output of wide-band pll vco2 selected by vco2 cs is 1/4 frequency-divided. output of wide-band pll vco2 selected by vco2 cs is 1/8 frequency-divided. 0 0 1 1 0 1 0 1 * this setting is valid only when the low-speed vco is selected by vco2 cs. ? 38 CXD3003r command bit processing xvco2 thru = 0 xvco2 thru = 1 v16m output is connected internally to vcki. v16m output is not connected internally. input the clock from vcki. command bit processing vco2 cs = 0 vco2 cs = 1 low-speed wide-band pll vco2 is selected. high-speed wide-band pll vco2 is selected. * this command sets internal or external connection for the vco2 used in cav-w mode. * the CXD3003r has two wide-band pll vco2, and this command selects one of these vco1. * block diagram for vco1 and vco2 including vcosel1, vcosel2, ksl0 to 3, vco1cs0, vco1cs1 and vco2 cs. * the CXD3003r has four multiplier pll vco1s, and this command selects one of these vco1s. four vcos are no.3, no.4, no.2 and no.1 in order of the maximum frequency. command bit vco1cs1 vco1cs0 processing no.1 (low-speed vco for CXD3003) no.2 (middle-speed vco for CXD3003) no.3 (high-speed vco for CXD3003) no.4 0 0 1 1 0 1 0 1 command data 4 mode specification vco1 cs1 vco1 cs0 xvco2 thru d11 d10 d9 d8 vco2 cs ? 39 CXD3003r * block diagram of vco internal path n o . 1 v c o 1 n o . 2 v c o 1 n o . 3 v c o 1 s e l e c t o r 1 / 2 1 / 1 1 / 8 1 / 4 s e l e c t o r t o d s p i n t e r i o r k s l 3 , 2 v c o 1 c s 1 , 0 v c o 1 s e l n o . 4 v c o 1 l o w - s p e e d v c o 2 h i g h - s p e e d v c o 2 s e l e c t o r 1 / 2 1 / 1 1 / 8 1 / 4 s e l e c t o r t o d s p i n t e r i o r k s l 1 , 0 v c o 2 c s v c o 2 s e l vco1 internal path vco2 internal path ? 40 CXD3003r command bit processing scor sel = 0 scor sel = 1 fsw signal is output. grscor (protected scor) is output. command bit processing scsy = 0 scsy = 1 no processing. grscor (protected scor) synchronization is applied again. * used when outputting grscor from the fsw pin. * used to resynchronize grscor. the rising edge signal of this command bit is used internally. therefore, when resynchronizing grscor, first return the setting to 0 and then set to 1. grscor achieves the crystal accuracy by removing the jitter components included in the scor signal. this signal is synchronized with pcmdata. the resynchronization conditions are when gtop = high or when the scsy pin = high. (same as when scsy = 1 is sent by the $8x command.) command data 5 mode specification erc4 scor sel scsy 0 d7 d6 d5 d4 command bit processing erc4 = 0 erc4 = 1 c2 error double correction is performed when dspb = 1. c2 error quadruple correction is performed when dspb = 1. ? 41 CXD3003r command data 1 function specification dclv on-off dspb on-off a.seq on-off d.pll on-off d23 d22 d21 d20 data 2 biligl main biligl sub flfc d19 d18 d17 xwoc d16 $9x commands command bit dclv on/off = 0 in clvs mode fsw = low, mon = high, mds = z; mdp = servo control signal, carrier frequency of 230hz at t b = 0 and 460hz at t b = 1. fsw = z, mon = high; mds = speed control signal, carrier frequency of 7.35khz; mdp = phase control signal, carrier frequency of 1.8khz. when dclv pwm and md = 1 (prohibited in clv-w and cav-w modes) mds = pwm polarity signal, carrier frequency of 132khz mdp = pwm absolute value output (binary), carrier frequency of 132khz when dclv pwm and md = 0 mds = z mdp = ternary pwm output, carrier frequency of 132khz in clvp mode in clvs and clvp modes dclv on/off = 1 (fsw, mon not required) clv mode contents when dclv on/off = 1 for the digital clv servo, the sampling frequency of the internal digital filter switches simultaneously with the clvp/clvs switching. therefore, the cut-off frequency for the clvs is fc = 70hz when t b = 0, and fc = 140hz when t b = 1. command bit dspb = 0 dspb = 1 normal-speed playback, c2 error quadruple correction. double-speed playback, c2 error double correction. (quadruple correction when erc4 = 1) processing flfc is normally 0. flfc is 1 in cav-w mode, for any playback speed. command bit dpll = 0 * dpll = 1 rfpll is analog. pdo, vcoi and vcoo are used. rfpll is digital. pdo is high impedance. meaning command bit biligl sub = 0 biligl sub = 1 stereo sub main mute biligl main = 0 biligl main = 1 definition of bilingual capable main, sub and stereo the left channel input is output to the left and right channels for main. the right channel input is output to the left and right channels for sub. the left and right channel inputs are output to the left and right channels for stereo. * external parts for the fili, filo and pco pins are required even when analog pll is selected. ? 42 CXD3003r command data 3 function specification dac emph dac att 0 0 d15 d14 d13 d12 these command bits control the dac. note) for normal stereo, channel 1 is the left channel and channel 2 is the right channel. command bit dac emph = 1 dac emph = 0 applies digital de-emphasis. the emphasis constants are t 1 = 50 s and t 2 = 15 s when fs = 44.1khz. turns digital de-emphasis off. processing command bit dac att = 1 dac att = 0 identical digital attenuation control is used for both channels 1 and 2. when common attenuation data is specified, the attenuation values for channel 1 are used. independent digital attenuation control is used for both channels 1 and 2. processing i/o sync circuit related pins: lrck and xwo, related command: xwoc during normal operation, the i/o sync circuit automatically synchronizes with the input lrck, and its operation proceeds in phase with the serial input data. however, there is a chance that synchronization will not be performed if there is a great deal of jitter in lrck, or if the power has just been turned on, etc. in this case, forced synchronization is possible by setting the xwo pin or command xwoc low (0) for 2/fs or more. forced synchronization must also be performed when switching the clock system such as when switching from clv mode to cav mode and vice versa, or when switching the operating frequency, etc. the forced synchronization operation is performed at the second rising edge of lrck after the xwo pin is set low or the xwoc command 19 set to 0. * this is used to perform resynchronization to dac. this command has the function equal to the external pin xwo's. set to high or 1 for the external pin or unused side of the command register. command bit external pin xwoc xwo processing dac sync window is open. dac sync window is not open. 0 0 1 1 l h l h ? 43 CXD3003r plm3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 mute l r l + r mute l r l + r mute l r l + r mute l r l + r mute mute mute mute l l l l r r r r l + r l + r l + r l + r mute reverse stereo mono plm2 plm1 plm0 channel 1 output channel 2 output remarks note) for normal stereo, channel 1 is the left channel and channel 2 is the right channel. the output data of l + r is (l + r)/2 to prevent overflow. dac play mode by controlling these command bits, the dac outputs channel 1 and channel 2 can be output in 16 different combinations of left channel, right channel, left + right channel, and mute. the relationship between the commands and the outputs is shown in the table on the following page. command data 4 function specification plm3 plm2 plm1 plm0 d11 d10 d9 d8 ? 44 CXD3003r command data 1 audio ctrl 0 0 mute att d23 d22 d21 d20 data 2 pct1 pct2 d19 d18 dads soc2 d17 d16 $ax commands command bit mute = 0 mute = 1 mute off if other mute conditions are not set. mute on. peak register reset. meaning command bit att = 0 att = 1 attenuation off ?2db meaning mute conditions (1) when register a mute = 1. (2) when mute pin = 1. (3) when register 8 d.out mute f = 1 and the digital out is on (md2 pin = 1). (4) when gfs stays low for over 35ms (during normal speed). (5) when register 9 biligl main = sub = 1. (6) when register a pct1 = 1 and pct2 = 0. (1) to (4) perform zero-cross muting with a 1ms time limit. command bit pct1 0 0 1 1 pct2 0 1 0 1 normal mode level meter mode peak meter mode normal mode 0db 0db mute 0db c1: double; c2: quadruple c1: double; c2: quadruple c1: double; c2: double c1: double; c2: double meaning pcm gain ecc error correction ability description of level meter mode (see timing chart 1-4.) when the lsi is set to this mode, it performs digital level meter functions. when the 96-bit clock is input to sqck, 96 bits of data are output to sqso. the initial 80 bits are sub q data (see ?. subcode interface). the last 16 bits are lsb first, which are 15-bit pcm data (absolute values) and an l/r flag. the l/r flag is high when the 15-bit pcm data is from the left channel and low when the data is from the right channel. the pcm data is reset and the l/r flag is reversed after one readout. then maximum value measuring continues until the next readout. ? 45 CXD3003r description of peak meter mode (see timing chart 1-5.) when the lsi is set to this mode, the maximum pcm data value is detected regardless of if it comes from the left or right channel. the 96-bit clock must be input to sqck to read out this data. when the 96-bit clock is input, 96 bits of data are output to sqso and the value is set in the lsi internal register again. in other words, the pcm maximum value detection register is not reset by the readout. to reset the pcm maximum value register to zero, set pct1 = pct2 = 0 or set the $ax mute. the sub q absolute time is automatically controlled in this mode. in other words, after the maximum value is generated, the absolute time for crc to become ok is retained in the memory. normal operation is conducted for the relative time. the final bit (l/r flag) of the 96-bit data is normally 0. the pre-value hold and average value interpolation data are fixed to level (? ) in this mode. sens output switching this command enables the sqso pin signal to be output from the sens pin. when soc2 = 0, sens output is performed as usual. when soc2 = 1, the sqso pin signal is output from the sens pin. at this time, the readout clock is input to the sclk pin. note) soc2 should be switched when sqck = sclk = high. command bit dads = 0 dads = 1 set to 0 when crystal = 33.8688mhz. set to 1 when crystal = 16.9344mhz. processing command bit soc2 = 0 soc2 = 1 the sens signal is output from the sens pin as usual. the sqso pin signal is output from the sens pin. processing ? 46 CXD3003r dac digital attenuator command data 3 d15 at1d 7 at1d 6 at1d 5 at1d 4 at1d 3 at1d 2 at1d 1 at1d 0 at2d 7 at2d 6 at2d 5 at2d 4 at2d 3 at2d 2 at2d 1 at2d 0 audio ctrl d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 data 4 data 5 data 6 note) at1d7 to at1d0 are the channel 1 att control bits. at2d7 to at2d0 are the channel 2 att control bits. command bits at1d7 to at1d0 (at2d7 to at2d0) ff (h) fe (h) 01 (h) 00 (h) 0db ?.034db ?8.131db ? audio output the attenuation data consists of 8 bits each for channels 1 and 2; the dac att bit can be used to control channels 1 and 2 with common attenuation data. (when common attenuation data is specified, the attenuation values for channel 1 are used.) an attenuation value, from 00 (h) to ff (h), is determined according to the following equation: att = 20 log [input data/255] db example: when the attenuation data is fa (h): att = 20 log [250/255] db = ?.172db soft mute with the soft mute function, when the attenuation data goes from ff (h) and 00 (h) and vice versa, muting is turned on and off over the muting time of 1024fs [s] = 23.2 [ms] (fs = 44.1khz). attenuation assume the attenuation data att1, att2 and att3, where att1 > att3 > att2. first, assume att1 is transferred and then att2 is transferred. if att2 is transferred before att1 is reached (state "a" in the diagram), then the value continues approaching att2. next, if att3 is transferred before att2 is reached (state "b" or "c" in the diagram), the attenuation begins approaching att3 from the current point. note that it takes 1024/fs [s] (fs = 44.1khz for cd players) to transit between attenuation data (from 0db to ? ). a t t 1 a b c a t t 2 0 d b a t t 3 handling of the attenuation value ? 47 CXD3003r $bx commands this command sets the traverse monitor count. command data 1 data 2 data 3 data 4 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 traverse monitor count setting when the set number of tracks are counted during fine search, the sled control for the traverse cycle control goes off. the traverse monitor count is set to monitor the traverse status from the sens output as comp and cout. ? 48 CXD3003r servo coefficient setting clv ctrl ($dx) gain mdp1 gain mdp0 gain mds1 gain mds0 gain clvs gain mds1 0 0 0 0 1 1 gain mds0 0 0 1 1 0 0 gain clvs 0 1 0 1 0 1 gclvs ?2db ?db ?db 0db 0db +6db command d23 data 1 d22 d21 d20 gain dclv0 gain dclv1 pcc1 pcc0 d19 data 2 description valid only when dclv = 1. valid when dclv = 1 or 0. d18 d17 d16 $cx commands the spindle servo gain is externally set when dclv = 1. clvs mode gain setting: gclvs note) when dclv = 0, the clvs gain is as follows. when gain clvs = 0, gclvs = ?2db. when gain clvs = 1, gclvs = 0db. gain mdp1 0 0 1 gain mdp0 0 1 0 gmdp ?db 0db +6db gain dclv1 0 0 1 gain dclv0 0 1 0 gdclv 0db +6db +12db gain mds1 0 0 1 gain mds0 0 1 0 gmds ?db 0db +6db clvp mode gain setting: gmdp: gmds dclv overall gain setting: gdclv command bit pcc1 pcc0 processing the vpco1 and 2 signals are output. the vpco1 and 2 pin outputs are high impedance. the vpco1 and 2 pin outputs are low. the vpco1 and 2 pin outputs are high. 0 0 1 1 0 1 0 1 this command controls the vpco1 and vpco2 pin signals. identical control can be performed for both vpco1 and vpco2 output with this setting. however, vpco2 can also be set to high impedance with the $e command fcsw separately from this setting. ? 49 CXD3003r $dx commands see "$cx commands". command bit dclv pwm md = 1 dclv pwm md = 0 digital clv pwm mode specified. both mds and mdp are used. clv-w and cav-w modes cannot be used. digital clv pwm mode specified. ternary mdp values are output. clv-w and cav-w modes can be used. description command bit tb = 0 tb = 1 tp = 0 tp = 1 bottom hold at a cycle of rfck/32 in clvs and clvh modes. bottom hold at a cycle of rfck/16 in clvs and clvh modes. peak hold at a cycle of rfck/4 in clvs mode. peak hold at a cycle of rfck/2 in clvs mode. description command data 1 clv ctrl dclv pwm md tb tp gain clvs d23 d22 d21 d20 command bit fcsw pcc1 pcc0 processing the vpco1 signal is output and the vpco2 pin is high impedance. the vpco1 and 2 pin outputs are high impedance. the vpco1 pin output is low and the vpco2 pin is high impedance. the vpco1 pin output is high and the vpco2 pin is high impedance. the vpco1 and 2 signals are output. the vpco1 and 2 pin outputs are high impedance. the vpco1 and 2 pin outputs are low. the vpco1 and 2 pin outputs are high. 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 processing for the $cx commands pcc1 and pcc2 and the $ex command fcsw is shown below. ? 50 CXD3003r the rotational velocity r of the spindle can be expressed with the following equation. r = l r: relative velocity at normal speed = 1 n: vp0 to 7 setting value l: multiple by vpctl0, 1 256 ?n 32 * the above setting should be 0, 0 except for the cav-w operating mode. command bit vpctl1 vpctl0 processing the setting of vp0 to 7 is multiplied by 1. the setting of vp0 to 7 is multiplied by 2. the setting of vp0 to 7 is multiplied by 3. the setting of vp0 to 7 is multiplied by 4. 0 0 1 1 0 1 0 1 command data 2 clv ctrl vp7 vp6 vp5 vp4 d19 d18 d17 d16 data 3 vp3 vp2 vp1 vp0 d15 d14 d13 d12 data 4 vp ctl1 vp ctl0 0 0 d11 d10 d9 d8 command bit processing vp0 to 7 the spindle rotational velocity is set. ? 51 CXD3003r command bit vp0 to 7 = f0 (h) : vp0 to 7 = e0 (h) : vp0 to 7 = c0 (h) : vp0 to 7 = a0 (h) : vp0 to 7 = 80 (h) : vp0 to 7 = 60 (h) : vp0 to 7 = 40 (h) vp0 to 7 = 20 (h) vp0 to 7 = 00 (h) playback at 1/2 (1, 2) speed to playback at 1 (2, 4) speed to playback at 2 (4, 8) speed to playback at 3 (6, 12) speed to playback at (8, 16) speed to playback at (10, 20) speed to playback at (12, 24) speed playback at (14, ? speed playback at (16, ? speed description notes) 1. values when crystal is 16.9344mhz and xtsl is low or when crystal is 33.8688mhz and xtls is high. 2. regarding the values in parentheses, the former ones are for when dspb = 1 and vpctl0, 1 = 0, and the latter ones are for when dspb = 1, vpctl0 = 1 and vpctl1 = 0. ? 52 CXD3003r e 0 c 0 a 0 8 0 2 4 6 8 r r e l a t i v e v e l o c i t y [ m u l t i p l e ] v p 0 t o 7 s e t t i n g v a l u e [ h e x ] 6 0 4 0 1 0 1 2 2 0 0 0 1 4 1 6 d s p b = 1 d s p b = 0 w h e n v p c t l 0 = v p c t l 1 = 0 e 0 c 0 a 0 8 0 4 8 1 2 1 6 r r e l a t i v e v e l o c i t y [ m u l t i p l e ] v p 0 t o 7 s e t t i n g v a l u e [ h e x ] 6 0 4 0 2 0 2 4 2 0 0 0 2 8 3 2 d s p b = 1 d s p b = 0 w h e n v p c t l 0 = 1 , v p c t l 1 = 0 ? 53 CXD3003r $ex commands command data 1 spd mode cm3 cm2 cm1 cm0 d23 d22 d21 d20 data 2 epwm spdc icap sfsl d19 d18 d17 d16 data 3 vc2c hifc lpwr vpon d15 d14 d13 d12 command bit cm3 cm2 cm1 description spindle stop mode. * spindle forward rotation mode. * spindle reverse rotation mode. valid only when lpwr = 0 in any mode. * rough servo mode. when the rf-pll circuit isn't locked, this mode is used to pull the disc rotations within the rf- pll capture range. pll servo mode. automatic clvs/clvp switching mode. used for normal playback. 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 1 1 cm0 0 0 0 0 1 0 mode stop kick brake clvs clvp clva * see timing charts 1-6 to 1-12. command bit epwm spdc icap sfsl vc2c hifc lpwr vpon inv vpco description crystal reference clv servo. used for playback in clv-w mode. * 1 spindle control with vp0 to 7. spindle control with the external pwm. vco control. * 2 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 mode clv-n clv-w cav-w cav-w vco-c * 1 figs. 3-1 and 3-2 show the control flow with the microcomputer software in clv-w mode. * 2 fig. 3-3 shows the control flow with the microcomputer software in vco-c mode. ? 54 CXD3003r mode dclv dclv pwm md lpwr command timing chart clv-n clv-w cav-w 0 1 1 1 0 0 1 0 0 0 0 0 0 1 0 1 kick brake stop kick brake stop kick brake stop kick brake stop kick brake stop kick brake stop kick brake stop 1-6 (a) 1-6 (b) 1-6 (c) 1-7 (a) 1-7 (b) 1-7 (c) 1-8 (a) 1-8 (b) 1-8 (c) 1-9 (a) 1-9 (b) 1-9 (c) 1-10 (a) 1-10 (b) 1-10 (c) 1-11 (a) 1-11 (b) 1-11 (c) 1-12 (a) 1-12 (b) 1-12 (c) mode dclv dclv pwm md lpwr timing chart clv-n clv-w cav-w 1 1 1 0 1 0 0 0 0 0 1 0 1 0 1 1-13 1-14 1-15 1-16 1-17 (epwm = 0) 1-18 (epwm = 0) 1-19 (epwm = 1) 1-20 (epwm = 1) note) clv-w and cav-w modes support control only by the ternary output of the mdp pin. therefore, set dclv to 1 and dclv pwm md to 0 in clv-w and cav-w modes. ? 55 CXD3003r command bit fcsw = 0 fcsw = 1 the vpco2 pin is not used and it is high impedance. the vpco2 pin is used and the pin signal is the same as vpco1. processing command spd mode data 4 this sets the gain when controlling the spindle with the phase comparator in cav-w mode. d11 d10 d9 d8 gain cav1 gain cav0 fcsw inv npco gain cav1 0 0 1 1 gain cav0 0 1 0 1 gain 0db ?db ?2db ?8db ? 56 CXD3003r timing chart 1-3 r c h 1 6 b i t c 2 p o i n t e r l c h 1 6 b i t c 2 p o i n t e r i f c 2 p o i n t e r = 1 , d a t a i s n g c 2 p o i n t e r f o r u p p e r 8 b i t s c 2 p o i n t e r f o r l o w e r 8 b i t s r c h c 2 p o i n t e r c 2 p o i n t e r f o r u p p e r 8 b i t s c 2 p o i n t e r f o r l o w e r 8 b i t s l c h c 2 p o i n t e r l r c k w d c k c d r o m = 0 c 2 p o c d r o m = 1 c 2 p o 4 8 b i t s l o t ? 57 CXD3003r timing chart 1-4 l e v e l m e t e r t i m i n g 9 6 c l o c k p u l s e s w f c k 1 2 3 9 6 c l o c k p u l s e s c r c f c r c f 1 2 3 p e a k d a t a o f t h i s s e c t i o n 1 6 b i t r / l l / r 9 6 b i t d a t a h o l d s e c t i o n 1 2 3 8 0 8 1 9 6 c r c f s q c k d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 1 3 d 1 4 l / r p e a k d a t a l / r f l a g s u b q d a t a s e e " s u b c o d e i n t e r f a c e " 1 5 - b i t p e a k - d a t a a b s o l u t e v a l u e d i s p l a y , l s b f i r s t 7 5 0 n s t o 1 2 0 s s q c k s q s o s q s o ? 58 CXD3003r timing chart 1-5 m e a s u r e m e n t p e a k m e t e r t i m i n g 9 6 c l o c k p u l s e s c r c f w f c k 1 2 3 m e a s u r e m e n t m e a s u r e m e n t 9 6 c l o c k p u l s e s c r c f c r c f 1 2 3 s q c k ? 59 CXD3003r timing chart 1-6 clv-n mode dclv = dclv pwm md = lpwr = 0 z k i c k m d s m d p h f s w l m o n h ( a ) k i c k z b r a k e m d s m d p f s w l m o n h ( b ) b r a k e z s t o p m d s m d p f s w l m o n ( c ) s t o p l l l timing chart 1-7 clv-n mode dclv = 1, dclv pwm md = lpwr = 0 z k i c k m d s m d p h f s w l m o n h ( a ) k i c k z b r a k e m d s m d p f s w l m o n h ( b ) b r a k e z s t o p m d s m d p f s w l m o n ( c ) s t o p z l z l z ? 60 CXD3003r timing chart 1-8 clv-n mode dclv = dclv pwm md = 1, lpwr = 0 k i c k m d s m d p h f s w l m o n h ( a ) k i c k b r a k e m d s m d p f s w l m o n h ( b ) b r a k e s t o p m d s m d p f s w l m o n ( c ) s t o p l l h l l l h timing chart 1-9 clv-w mode (when following the spindle rotational velocity) dclv = 1, dclv pwm md = lpwr = 0 z k i c k m d s m d p h f s w l m o n h ( a ) k i c k z b r a k e m d s m d p f s w l m o n h ( b ) b r a k e z s t o p m d s m d p f s w l m o n ( c ) s t o p z l z o t h e r t h a n w h e n f o l l o w i n g t h e v e l o c i t y , t h e t i m i n g i s t h e s a m e a s t i m i n g c h a r t 1 - 6 ( a ) . l z o t h e r t h a n w h e n f o l l o w i n g t h e v e l o c i t y , t h e t i m i n g i s t h e s a m e a s t i m i n g c h a r t 1 - 6 ( b ) . ? 61 CXD3003r timing chart 1-10 clv-w mode (when following the spindle rotational velocity) dclv = 1, dclv pwm md = 0, lpwr = 1 z k i c k m d s m d p h f s w l m o n h ( a ) k i c k z b r a k e m d s m d p f s w l m o n h ( b ) b r a k e z z s t o p m d s m d p f s w l m o n ( c ) s t o p z l z o t h e r t h a n w h e n f o l l o w i n g t h e v e l o c i t y , t h e t i m i n g i s t h e s a m e a s t i m i n g c h a r t 1 - 6 ( a ) . timing chart 1-11 cav-w mode dclv = 1, dclv pwm md = lpwr = 0 z k i c k m d s m d p h f s w l m o n h ( a ) k i c k z b r a k e m d s m d p f s w l m o n h ( b ) b r a k e z s t o p m d s m d p f s w l m o n ( c ) s t o p z l h ? 62 CXD3003r timing chart 1-12 cav-w mode dclv = 1, dclv pwm md = 0, lpwr = 1 z k i c k m d s m d p h f s w l m o n h ( a ) k i c k z b r a k e m d s m d p f s w l m o n h ( b ) b r a k e z z s t o p m d s m d p f s w l m o n ( c ) s t o p z h timing chart 1-13 clv-n mode dclv pwm md = lpwr = 0 z m d s m d p a c c e l e r a t i o n z d e c e l e r a t i o n 1 3 2 k h z 7 . 6 s n 2 3 6 ( n s ) n = 0 t o 3 1 timing chart 1-14 clv-n mode dclv pwm md = 1, lpwr = 0 m d s m d p a c c e l e r a t i o n d e c e l e r a t i o n 1 3 2 k h z 7 . 6 s n 2 3 6 ( n s ) n = 0 t o 3 1 o u t p u t w a v e f o r m s w i t h d c l v = 1 ? 63 CXD3003r timing chart 1-15 clv-w mode dclv pwm md = lpwr = 0 z m d s m d p a c c e l e r a t i o n z d e c e l e r a t i o n 1 3 2 k h z 3 . 8 s o u t p u t w a v e f o r m s w i t h d c l v = 1 timing chart 1-16 clv-w mode dclv pwm md = 0, lpwr = 1 z m d s m d p a c c e l e r a t i o n z 1 3 2 k h z 3 . 8 s o u t p u t w a v e f o r m s w i t h d c l v = 1 t h e b r a k e p u l s e i s m a s k e d w h e n l p w r = 1 . timing chart 1-17 cav-w mode epwm = dclv pwm md = lpwr = 0 m d p a c c e l e r a t i o n z d e c e l e r a t i o n 2 6 4 k h z 3 . 8 s timing chart 1-18 cav-w mode epwm = dclv pwm md = 0, lpwr = 1 m d p a c c e l e r a t i o n z 2 6 4 k h z 3 . 8 s t h e b r a k e p u l s e i s m a s k e d w h e n l p w r = 1 . ? 64 CXD3003r timing chart 1-19 cav-w mode epwm = 1, dclv pwm md = lpwr = 0 p w m i m d p h l h l a c c e l e r a t i o n d e c e l e r a t i o n timing chart 1-20 cav-w mode epwm = 1, dclv pwm md = 0, lpwr = 1 p w m i m d p h l h z a c c e l e r a t i o n t h e b r a k e p u l s e i s m a s k e d w h e n l p w r = 1 . note) clv-w and cav-w modes support control only by the ternary output of the mdp pin. therefore, set dclv pwm md to 0 in clv-w and cav-w modes. ?65 CXD3003r [2] subcode interface there are two methods for reading out a subcode externally. the 8-bit subcodes p to w can be read out from sbso by inputting exck. sub q can be read out after checking crc of the 80 bits in the subcode frame. sub q can be read out from the sqso pin by inputting 80 clock pulses to the sqck pin when scor comes correctly and crcf is high. ?-1. p to w subcode readout data can be read out by inputting exck immediately after wfck falls. (see timing chart 2-1.) ?-2. 80-bit sub q readout fig. 2-2 shows the peripheral block of the 80-bit sub q register. first, sub q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the crc check circuit. 96-bit sub q is input, and if the crc is ok, it is output to sqso with crcf = 1. in addition, 80 bits are loaded into the parallel/serial register. when sqso goes high after scor is output, the cpu determines that new data (which passed the crc check) has been loaded. when the 80-bit data is loaded, the order of the msb and lsb is inverted within each byte. as a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered lsb first. once the 80-bit data load is confirmed, sqck is input so that the data can be read. the sqck input is detected, and the retriggerable monostable multivibrator is reset while the input is low. the retriggerable monostable multivibrator has a time constant from 270 to 400 s. when the duration when sqck is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the serial/parallel register is not loaded into the parallel/serial register. while the monostable multivibrator is being reset, data cannot be loaded in the peak detection parallel/serial register or the 80-bit parallel/serial register. in other words, while reading out with a clock cycle shorter than this time constant, the register will not be rewritten by crcok and others. the previously mentioned peak detection register can be connected to the shift-in of the 80-bit parallel/serial register. for ring control 1, input and output are shorted during peak meter and level meter modes. for ring control 2, input and output are shorted during peak meter mode. this is because the register is reset with each readout in level meter mode, and to prevent readout destruction in peak meter mode. as a result, the 96-bit clock must be input in peak meter mode. the absolute time after peak is stored in the memory in peak meter mode. (see timing chart 2-3.) the high and low intervals for sqck should be between 750ns and 120 s. ? 66 CXD3003r timing chart 2-1 i n t e r n a l p l l c l o c k 4 . 3 2 1 8 d m h z w f c k s c o r e x c k s b s o 7 5 0 n s m a x s 0 s 1 q r w f c k s c o r e x c k s b s o s 0 s 1 q r s t u v w s 0 s 1 p 1 q r s t u v w p 1 p 2 p 3 s a m e s a m e s u b c o d e p . q . r . s . t . u . v . w r e a d t i m i n g ? 67 CXD3003r block diagram 2-2 8 8 8 8 8 8 8 8 8 o r d e r i n v e r s i o n 1 6 p e a k d e t e c t i o n l o a d c o n t r o l r i n g c o n t r o l 2 c r c f m i x m o n o s t a b l e m u l t i v i b r a t o r c r c c a b s t i m e l o a d c o n t r o l f o r p e a k v a l u e 1 6 b i t p / s r e g i s t e r r i n g c o n t r o l 1 s o s i s q s o s q c k s h i f t s h i f t s u b q l d l d l d l d l d l d l d l d s o h g f e d c b a a b c d e f g h s i 8 0 b i t p / s r e g i s t e r 8 0 b i t s / p r e g i s t e r ( a f r a m ) ( a s e c ) ( a m i n ) a d d r s c t r l s i n s u b q ? 68 CXD3003r timing chart 2-3 1 2 3 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 w f c k s c o r s q s o s q c k m o n o s t a b l e m u l t i v i b r a t o r ( i n t e r n a l ) c r c f 1 d e t e r m i n e d b y m o d e c r c f 2 8 0 o r 9 6 c l o c k r e g i s t e r l o a d f o r b i d d e r 2 7 0 t o 4 0 0 s w h e n s q c k = h i g h . 7 5 0 n s t o 1 2 0 s 3 0 0 n s m a x c r c f a d r 0 a d r 1 a d r 2 a d r 3 c t l 0 c t l 1 c t l 2 c t l 3 s q c k s q s o 1 2 3 c r c f 1 ? 69 CXD3003r timing chart 2-4 e x a m p l e : $ 8 0 2 0 0 0 l a t c h s e t s q c k h i g h d u r i n g t h i s i n t e r v a l . i n t e r n a l s i g n a l l a t c h p e r 0 p e r 1 p e r 2 p e r 3 p e r 4 p e r 5 p e r 6 p e r 7 c 1 f 0 c 1 f 1 c 1 f 2 c 2 f 0 c 2 f 1 c 2 f 2 f o k g f s l o c k e m p h 7 5 0 n s o r m o r e x l a t s q c k s q s o a l o c k v f 0 v f 1 v f 2 v f 3 v f 4 v f 5 v f 6 v f 9 v f 7 v f 8 signal per0 to 7 fok gfs lock emph alock vf0 to 9 rf jitter amount (used to adjust the focus bias). 8-bit binary data in per0 = lsb, per7 = msb. focus ok high when the frame sync and the insertion protection timing match. gfs is sampled at 460hz; when gfs is high, this pin outputs a high signal. if gfs is low eight consecutive samples, this pin ou tputs low. high when the playback disc has emphasis. gfs is sampled at 460hz; when gfs is high eight consecutive samples, this pin outputs a high signal. if gfs is low eight consec utive samples, this pin outputs low. used in cav-w mode. the result obtained by measuring the rotational velocity of the disc. (see timing chart 2-5.) vf0 = lsb, vf 7 = msb. description c1f2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 no c1 errors; c1 pointer reset one c1 error corrected; c1 pointer reset no c1 errors; c1 pointer set one c1 error corrected; c1 pointer set two c1 errors corrected; c1 pointer set c1 correction impossible; c1 pointer set c1f1 c1f0 description c2f2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 no c2 errors; c2 pointer reset one c2 error corrected; c2 pointer reset two c2 errors corrected; c2 pointer reset three c2 errors corrected; c2 pointer reset four c2 errors corrected; c2 pointer reset c2 correction impossible; c1 pointer copy c2 correction impossible; c2 pointer set c2f1 c2f0 description ? 70 CXD3003r timing chart 2-5 m e a s u r e m e n t i n t e r v a l ( a p p r o x i m a t e l y 3 . 8 s ) r e f e r e n c e w i n d o w ( 1 3 2 . 2 k h z ) m e a s u r e m e n t p u l s e ( v 1 6 m / 2 ) m e a s u r e m e n t c o u n t e r v f 0 t o 9 l o a d m the relative velocity of the disc can be obtained with the following equation. r = (r: relative velocity, m: measurement results) vf0 to 9 is the result obtained by counting vlki/2 pulses while the reference signal (132.2khz) generated from xtal (xtli, xtlo) (384fs) is high. this value is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when dspb is low). m + 1 32 ? 71 CXD3003r [3] description of modes this lsi has three basic operating modes using a combination of spindle control and the pll. the operations for each mode are described below. ?-1. clv-n mode this mode is compatible with the cxd2510q, and operation is the same as for conventional control (however, variable pitch cannot be used). the pll capture range is 150khz. ?-2. clv-w mode this is the wide capture range mode. this mode allows pll to follow the rotational velocity of the disc. this rotational following control has two types: using the built-in vco2 or providing an external vco. the spindle is the same clv servo as for the conventional series. operation using the built-in vco2 is described below. (when using an external vco, input the signal from the vpco pin to the low-pass filter, use the output from the low-pass filter as the control voltage for the external vco, and input the oscillation from the vco to the vcki pin.) when starting to rotate the disc and/or speeding up to the lock range from the condition where the disc is stopped, cav-w mode should be used. specifically, first send $e665x to set cav-w mode and kick the disc, then send $e60cx to set clv-w mode if alock is high, which can be read out serially from the sqso pin. clv-w mode can be used while alock is high. the microcomputer monitors the serial data output, and must return the operation to the speed adjusting state (cav-w mode) when alock becomes low. the control flow according to the microcomputer software in clv-w mode is shown in fig. 3-2. in clv-w mode (normal), low power consumption is achieved by setting lpwr to high. control was formerly performed by applying acceleration and deceleration pulses to the spindle motor. however, when lpwr is set high, deceleration pulses are not output, thereby achieving low power consumption mode. clv-w mode supports control only by the ternary output of the mdp pin. therefore, when using clv-w mode, set dclv pwm md to low. note) the capture range for this mode is theoretically up to the signal processing limit. ?-3. cav-w mode this is cav mode. in this mode, the external clock is fixed and it is possible to control the spindle to the desired rotational velocity. the rotational velocity is determined by the vp0 to 7 setting values or the external pwm. when controlling the spindle with vp0 to 7, setting cav-w mode with the $e665x command and controlling vp0 to 7 with the $dx commands allows the rotational velocity to be varied from low speed to 20 speed. (see "$dx commands".) also, when controlling the spindle with the external pwm, the pwmi pin is binary input which becomes kick during high intervals and brake during low intervals. the microcomputer can know the rotational velocity using v16m. the reference frequency for the velocity measurement is a signal of 132.3khz obtained by dividing xtal (xtli, xtlo) (384fs) by 128. the velocity is obtained by counting v16m/2 pulses while the reference is high, and the result is output from the new cpu interface as 10 bits (vp0 to 9). these measurement results are 31 when the disc is rotating at normal speed or 127 when it is rotating at quadruple speed. these values match those of the 256 - n for control with vp0 to 7. (see table 2-5 and fig. 2-6.) in cav-w mode, the spindle is set to the desired rotational velocity and the operation speed for the entire system follows this rotational velocity. therefore, the cycles for the fs system clock, pcm data and all other output signals from this lsi change according to the rotational velocity of the disc. note) the capture range for this mode is theoretically up to the signal processing limit. note) set flfc to 1 for this mode ? 72 CXD3003r c a v - w c l v s c l v - w c l v p r o t a t i o n a l v e l o c i t y t a r g e t s p e e d o p e r a t i o n m o d e s p i n d l e m o d e t i m e k i c k l o c k a l o c k fig. 3-1. disc stop to regular playback in clv-w mode ?-4. vco-c mode this is the vco control mode. in this mode, the v16m oscillation frequency can be controlled by setting vp0 to 7, vpctl0 and 1 of $d. v16m = n: setting value of vp0 to 7 1: setting value of vpctl0 and 1 v16m determines the vco1 oscillation frequency. the vco1 frequency can be expressed with the following equations. dspb = 0 vco1 = v16m dspb = 1 vco1 = v16m 1 (256 ?n) 32 49 24 49 16 ? 73 CXD3003r clv-w mode n o y e s k i c k $ e 8 0 0 0 m u t e o f f $ a 0 0 x x x x a l o c k = h ? n o y e s a l o c k = l ? c l v - w m o d e s t a r t c a v - w $ e 6 6 5 x ( c l v a ) c l v - w $ e 6 c 0 0 ( c l v a ) ( w f c k p l l ) fig. 3-2. clv-w mode flow chart vco-c mode r ? ( w h a t m i n u t e s f o r a b s o l u t e t i m e ? ) n ? ( c a l c u l a t e s n ) t r a n s f e r $ e 0 0 5 1 0 t r a n s f e r $ d x x x t r a c k j u m p s u b r o u t i n e ? w h a t m u l t i p l e s p e e d i s t h i s e q u i v a l e n t t o a t a r r i v a l ? ? c a l c u l a t e s v p 0 t o 7 . ? s w i t c h e s t o v c o c o n t r o l m o d e . e p w m = s p d c = i c a p = s f s l = v c 2 c = l p w r = 0 , h i f c = v p o n = 1 ? t r a n s f e r s v p 0 t o 7 . ( e q u i v a l e n t t o v p 0 t o 7 ) ? s w i t c h e s t o n o r m a l - s p e e d p l a y b a c k m o d e . e p w m = s f s l = v c 2 c = l p w r = 0 , s p d c = i c a p = h i f c = v p o n = 1 a c c e s s s t a r t a c c e s s e n d t r a n s f e r $ e 6 6 5 0 0 fig. 3-3. access flow chart using vco control ? 74 CXD3003r [4] description of other functions ?-1. channel clock regeneration by the digital pll circuit the channel clock is necessary for demodulating the efm signal regenerated by the optical system. assuming t as the channel clock cycle, the efm signal is modulated in an integer multiple of t from 3t to 11t. in order to read the information in the efm signal, this integer value must be read correctly. as a result, t, that is the channel clock, is necessary. in an actual player, a pll is necessary for regenerating the channel clock because the fluctuation in the spindle rotation alters the width of the efm signal pulses. the block diagram of this pll is shown in fig. 4-1. the CXD3003r has a built-in three-stage pll. the first-stage pll is a wide-band pll. when using the internal vco2, an external lpf is necessary; when not using the internal vco2, external lpf and vco are necessary. the output of this first-stage pll is used as a reference for all clocks within the lsi. the second-stage pll regenerates the high-frequency clock needed by the third-stage digital pll. the third-stage pll is a digital pll that regenerates the actual channel clock. the digital pll in clv-n mode has a secondary loop, and is controlled by the primary loop (phase) and the secondary loop (frequency). when flfc = 1, the secondary loop can be turned off. high frequency components such as 3t and 4t may contain deviations. in such as case, turning the secondary loop off yields better playability. however, in this case the capture range becomes 50khz. a new digital pll has been provided for clv-w mode to follow the rotational velocity of the disc in addition to the conventional secondary loop. ? 75 CXD3003r block diagram 4-1 x t s l 1 / 2 1 / 3 2 1 / n 1 / 2 m i c r o c o m p u t e r c o n t r o l n = 1 t o 2 5 6 ( v p 7 t o 0 ) 1 / k ( k s l 1 , 0 ) c l v - w c a v - w s p i n d l e r o t a t i o n i n f o r m a t i o n c l v - n c l v - w c a v - w / c l v - n p h a s e c o m p a r a t o r s e l e c t o r l p f 2 / 1 m u x v p o n 1 / m 1 / n v c o s e l 2 v c o 2 p h a s e c o m p a r a t o r v c o 1 v c o s e l 1 1 / k ( k s l 3 , 2 ) d i g i t a l p l l r f p l l v p c o 1 t o 2 v c t l v 1 6 m v c k i p c o f i l i f i l o c l t v x t l i c l o c k i n p u t 1 / l l = 1 , 2 , 3 , 4 ( v p c t l 0 , 1 ) ? 76 CXD3003r ?-2. frame sync protection in normal-speed playback, a frame sync is recorded approximately every 136 s (7.35khz). this signal is used as a reference to recognize the data within a frame. conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized. as a result, recognizing the frame sync properly is extremely important for improving playability. in the CXD3003r, window protection and forward protection/backward protection have been adopted for frame sync protection. these functions achieve very powerful frame sync protection. there are two window widths; one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (wsel = 0/1). in addition, the forward protection counter is fixed to 13, and the backward protection counter to 3. concretely, when the frame sync is being played back normally and then cannot be detected due to scratches, a maximum of 13 frames are inserted. if the frame sync cannot be detected for 13 frames or more, the window opens to resynchronize the frame sync. in addition, immediately after the window opens and the resynchronization is executed, if a proper frame sync cannot be detected within 3 frames, the window opens immediately. ?-3. error correction in the cd format, one 8-bit data contains two error correction codes, c1 and c2. for c1 correction, the code is created with 28-byte information and 4-byte c1 parity. for c2 correction, the code is created with 24-byte information and 4-byte parity. both c1 and c2 are reed solomon codes with a minimum distance of 5. the CXD3003r uses refined super strategy to achieve double correction for c1 and quadruple correction for c2. in addition, to prevent c2 miscorrection, a c1 pointer is attached to data after c1 correction according to the c1 error status, the playback status of the efm signal, and the operating status of the player. the correction status can be monitored externally. see table 4-2. when the c2 pointer is high, the data in question was uncorrectable. either the pre-value was held or an average value interpolation was made for the data. mnt3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 no c1 errors; c1 pointer reset one c1 error corrected; c1 pointer reset no c1 errors; c1 pointer set one c1 error corrected; c1 pointer set two c1 errors corrected; c1 pointer set c1 correction impossible; c1 pointer set no c2 errors; c2 pointer reset one c2 error corrected; c2 pointer reset two c2 errors corrected; c2 pointer reset three c2 errors corrected; c2 pointer reset four c2 errors corrected; c2 pointer reset c2 correction impossible; c1 pointer copy c2 correction impossible; c2 pointer set mnt2 mnt1 mnt0 description table 4-2. ? 77 CXD3003r timing chart 4-3 n o r m a l - s p e e d p b 4 0 0 t o 5 0 0 n s r f c k m n t 3 m n t 1 m n t 0 t = d e p e n d e n t o n e r r o r c o n d i t i o n c 1 c o r r e c t i o n c 2 c o r r e c t i o n s t r o b e s t r o b e m n t 2 ?-4. da interface the CXD3003r has two da interface modes. a) 48-bit slot interface this interface includes 48 cycles of the bit clock within one lrck cycle, and is msb first. when lrck is high, the data is for the left channel. b) 64-bit slot interface this interface includes 64 cycles of the bit clock within one lrck cycle, and is lsb first. when lrck is low, the data is for the left channel. ? 78 CXD3003r timing chart 4-4 l r c k ( 4 4 . 1 k ) d a 1 5 ( 2 . 1 2 m ) w d c k d a 1 6 l r c k ( 8 8 . 2 k ) d a 1 5 ( 4 . 2 3 m ) w d c k d a 1 6 4 8 - b i t s l o t n o r m a l - s p e e d p l a y b a c k p s s l = l 1 2 4 r 0 l c h m s b ( 1 5 ) l 1 4 l 1 3 l 1 2 l 1 1 l 1 0 l 9 l 8 l 7 l 6 l 5 l 4 l 3 l 2 l 1 l 0 r c h m s b l c h m s b ( 1 5 ) 2 4 r c h m s b 2 3 4 5 6 7 8 9 1 0 1 1 1 2 4 8 - b i t s l o t d o u b l e - s p e e d p l a y b a c k 1 2 l 0 r 0 ? 79 CXD3003r timing chart 4-5 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 r 1 5 l c h l s b r c h l s b ( 0 ) 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 2 0 3 0 3 2 3 1 d a 1 2 ( 4 4 . 1 k ) d a 1 3 ( 2 . 8 2 m ) d a 1 4 6 4 - b i t s l o t n o r m a l s p e e d p l a y b a c k p s s l = l 1 l c h l s b 1 2 3 4 5 1 0 1 5 2 5 d a 1 2 ( 8 8 . 2 k ) d a 1 3 ( 5 . 6 4 m ) d a 1 4 6 4 - b i t s l o t d o u b l e - s p e e d p l a y b a c k 2 0 3 0 3 1 3 2 r c h l s b ( 0 ) 2 3 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 4 l 1 5 ? 80 CXD3003r ?-5. digital out there are three digital out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. the CXD3003r supports type 2 form 1. the channel status clock accuracy is automatically set to level ii when using the crystal clock and to level iii in cav-w mode. in addition, sub q data which are matched twice in succession after a crc check are input to the first four bits (bits 0 to 3). dout is output when the crystal is 34mhz and dspb is set to 1 with xtsl high in clv-n or clv-w mode. therefore, set md2 to 0 and turn dout off. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 / 1 0 0 0 i d 0 i d 1 c o p y e m p h 0 0 0 0 1 0 0 0 0 0 0 0 f r o m s u b q 0 1 6 3 2 4 8 1 7 6 s u b q c o n t r o l b i t s t h a t m a t c h e d t w i c e w i t h c r c o k d i g i t a l o u t c b i t 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 v p o n : 1 c r y s t a l : 0 b i t s 0 t o 3 b i t 2 9 table 4-6. ? 81 CXD3003r ?-6. servo auto sequence this function performs a series of controls, including auto focus and track jumps. when the auto sequence command is received from the cpu, auto focus, 1-track jump, 2n-track jump, fine search and m-track move are executed automatically. the servo is used in an exclusive manner during the auto sequence execution (when xbusy = low), so that commands from the cpu are not transferred to the servo, but can be sent to the CXD3003r. in addition, when using the auto sequence, turn the a.seq of register 9 on. when clok goes from low to high while xbusy is low, xbusy does not become high for a maximum of 100 s after that point. this is to prevent the transfer of erroneous data to the servo when xbusy changes from low to high by the monostable multivibrator, which is reset by clok being low (when xbusy is low). in addition, a max timer is built into this lsi as a countermeasure against abnormal operation due to external disturbances, etc. when the auto sequence command is sent from the cpu, this command assumes a $4xy format, in which x specifies the command and y sets the max timer value and timer range. if the executed auto sequence command does not terminate within the set timer value, the auto sequence is interrupted (like $40). see [1] "$4x commands" concerning the timer value and range. also, the max timer is invalidated by inputting $4x0. although this command is explained in the format of $4x in the following command descriptions, the timer value and timer range are actually sent together from the cpu. (a) auto focus ($47) focus search-up is performed, fok and fzc are checked, and the focus servo is turned on. if $47 is received from the cpu, the focus servo is turned on according to fig. 4-8. the auto focus starts with focus search-up, and note that the pickup should be lowered beforehand (focus search-down). in addition, blind e of register 5 is used to eliminate fzc chattering. concretely, the focus servo is turned on at the falling edge of fzc after fzc has been continuously high for a longer time than e. (b) track jump 1, 10 and 2n-track jumps are performed respectively. always use this when the focus, tracking, and sled servos are on. note that tracking gain-up and braking-on ($17) should be sent beforehand because they are not involved in this sequence. 1-track jump when $48 ($49 for rev) is received from the cpu, a fwd (rev) 1-track jump is performed in accordance with fig. 4-9. set blind a and brake b with register 5. 10-track jump when $4a ($4b for rev) is received from the cpu, a fwd (rev) 10-track jump is performed in accordance with fig. 4-10. the principal difference from the 1-track jump is to kick the sled. in addition, after kicking the actuator, when 5 tracks have been counted through cout, the brake is applied to the actuator. then, when the actuator speed is found to have slowed up enough (determined by the cout cycle becoming longer than the overflow c set with register 5), the tracking and sled servos are turned on. ? 82 CXD3003r 2n-track jump when $4c ($4d for rev) is received from the cpu, a fwd (rev) 2n-track jump is performed in accordance with fig. 4-11. the track jump count n is set with register 7. although n can be set to 216 tracks, note that the setting is actually limited by the actuator. cout is used for counting the number of jumps when n is less than 16, and mirr is used with n is 16 or more. although the 2n-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "d", set with register 6. fine search when $44 ($45 for rev) is received from the cpu, a fwd (rev) fine search (n-track jump) is performed in accordance with fig. 4-12. the differences from a 2n-track jump are that a higher precision is achieved by controlling the traverse speed, and a longer distance jump achieved by controlling the sled. the track jump count is set with register 7. n can be set to 216 tracks. after kicking the actuator and sled, the traverse speed is controlled based on the overflow g. set kick d and f with register 6 and overflow g with register 5. also, sled speed control during traverse can be turned off by causing comp to fall. set the number of tracks during which comp falls with register b. after n tracks have been counted through cout, the brake is applied to the actuator and sled. (this is performed by turning on the tracking servo for the actuator, and by kicking the sled in the opposite direction during the time for kick d set with register 6.) then, the tracking and sled servos are turned on. set overflow g to the speed required to slow up just before the track jump terminates. (the speed should be such that it will come on-track when the tracking servo turns on at the termination of the track jump.) for example, set the target track count n ? a for the traverse monitor counter which is set with register b, and comp will be monitored. when the falling edge of this comp is detected, overflow g can be reset. ? 83 CXD3003r a u t o f o c u s f o c u s s e a r c h u p f o k = h n o y e s f z c = h n o y e s f z c = l n o y e s e n d f o c u s s e r v o o n c h e c k w h e t h e r f z c i s c o n t i n u o u s l y h i g h f o r t h e p e r i o d o f t i m e e s e t w i t h r e g i s t e r 5 . fig. 4-8-(a). auto focus flow chart x l a t $ 4 7 l a t c h $ 0 3 b l i n d e $ 0 8 f o k s e i n ( f z c ) b u s y c o m m a n d f o r s s p fig. 4-8-(b). auto focus timing chart ? 84 CXD3003r 1 t r a c k n o y e s e n d t r a c k k i c k s l e d s e r v o w a i t ( b l i n d a ) c o u t = t r a c k r e v k i c k w a i t ( b r a k e b ) t r a c k s l e d s e r v o o n f w d k i c k f o r r e v j u m p r e v k i c k f o r r e v j u m p fig. 4-9-(a). 1-track jump flow chart x l a t c o u t b u s y c o m m a n d f o r s s p $ 4 8 ( r e v = $ 4 9 ) l a t c h $ 2 8 ( $ 2 c ) b l i n d a b r a k e b $ 2 c ( $ 2 8 ) $ 2 5 fig. 4-9-(b). 1-track jump timing chart ? 85 CXD3003r 1 0 t r a c k n o y e s e n d t r a c k , s l e d f w d k i c k w a i t ( b l i n d a ) c o u t = 5 ? t r a c k , r e v k i c k t r a c k , s l e d s e r v o o n c h e c k w h e t h e r t h e c o u t c y c l e i s l o n g e r t h a n o v e r f l o w c . c o u n t s c o u t 5 n o y e s c = o v e r f l o w ? fig. 4-10-(a). 10-track jump flow chart c o u t $ 4 a ( r e v = $ 4 b ) l a t c h b l i n d a $ 2 a ( $ 2 f ) c o u t 5 c o u n t $ 2 e ( $ 2 b ) o v e r f l o w c $ 2 5 x l a t b u s y c o m m a n d f o r s s p fig. 4-10-(b). 10-track jump timing chart ? 86 CXD3003r 2 n t r a c k n o y e s e n d t r a c k , s l e d f w d k i c k w a i t ( b l i n d a ) c o u t ( m i r r ) = n t r a c k r e v k i c k t r a c k s e r v o o n n o y e s c = o v e r f l o w w a i t ( k i c k d ) s l e d s e r v o o n c o u n t s c o u t f o r t h e f i r s t 1 6 t i m e s a n d m i r r f o r m o r e t i m e s . fig. 4-11-(a). 2n-track jump flow chart x l a t b l i n d a $ 2 a ( $ 2 f ) c o u t ( m i r r ) n c o u n t $ 2 e ( $ 2 b ) o v e r f l o w c k i c k d $ 2 6 ( $ 2 7 ) $ 2 5 $ 4 c ( r e v = $ 4 d ) l a t c h c o u t ( m i r r ) b u s y c o m m a n d f o r s s p fig. 4-11-(b). 2n-track jump timing chart ? 87 CXD3003r t r a c k s e r v o o n s l e d f w d k i c k f i n e s e a r c h w a i t ( k i c k d ) t r a c k s l e d f w d k i c k w a i t ( k i c k f ) t r a v e r s e s p e e d c t r l ( o v e r f l o w g ) c o u t = n ? t r a c k s e r v o o n s l e d r e v k i c k w a i t ( k i c k d ) t r a c k s l e d s e r v o o n e n d y e s n o fig. 4-12-(a). fine search flow chart t r a v e r s e s p e e d c o n t r o l ( o v e r f l o w g ) & c o u t n c o u n t k i c k f k i c k d $ 2 6 ( $ 2 7 ) $ 2 a ( $ 2 f ) $ 2 7 ( $ 2 6 ) $ 2 5 $ 4 4 ( r e v = $ 4 5 ) l a t c h x l a t c o u t k i c k d b u s y fig. 4-12-(b). fine search timing chart ? 88 CXD3003r m t r a c k m o v e n o y e s e n d t r a c k s e r v o o f f s l e d f w d k i c k w a i t ( b l i n d a ) c o u t ( m i r r ) = m t r a c k , s l e d s e r v o o f f c o u n t s c o u t f o r m < 1 6 . c o u n t s m i r r f o r m 3 1 6 . fig. 4-13-(a). m-track move flow chart x l a t b l i n d a $ 2 2 ( $ 2 3 ) c o u t ( m i r r ) m c o u n t $ 2 0 $ 4 e ( r e v = $ 4 f ) l a t c h c o u t ( m i r r ) b u s y c o m m a n d f o r s e r v o fig. 4-13-(b). m-track move timing chart ? 89 CXD3003r ?-7. digital clv fig. 4-14 shows the block diagram. digital clv outputs mds error and mdp error signals with pwm, with the sampling frequency increased up to 130khz during normal-speed playback in clvs, clvp and other modes. in addition, the digital spindle servo gain is variable. m d p d i g i t a l c l v c l v s u / d m d s e r r o r m d p e r r o r c l v p / s m e a s u r e m e a s u r e 2 / 1 m u x o v e r s a m p l i n g f i l t e r - 1 g a i n m d s 1 / 2 m u x c l v p / s o v e r s a m p l i n g f i l t e r - 2 n o i s e s h a p e m o d u l a t i o n k i c k , b r a k e , s t o p m d s m o d e s e l e c t g a i n d c l v g a i n m d p d c l v m d , l p w r p w m i fig. 4-14. block diagram clvs u/d : up/down signal from clvs servo mds error: frequency error for clvp servo mdp error: phase error for clvp servo pwmi: spindle drive signal from the microcomputer for cav servo ? 90 CXD3003r ?-8. playback speed in the CXD3003r, the following playback modes can be selected through different combinations of xtli, xtsl pin, double-speed command (dspb), vco1 selection command (vcosel1), vco1 frequency division commands (ksl3, ksl2) and command transfer rate selector (ashs) in clv-n or clv-w mode. mode 1 2 3 4 5 6 7 xtli 768fs 768fs 768fs 768fs 384fs 384fs 384fs xtsl 1 1 0 0 0 0 1 dspb 0 1 0 1 0 1 1 vcosel1 * 1 0/1 0/1 1 1 0/1 0/1 0/1 ashs 0 0 1 1 0 0 0 playback speed 1 2 2 4 1 2 1 error correction c1: double; c2: quadruple c1: double; c2: double c1: double; c2: quadruple c1: double; c2: double c1: double; c2: quadruple c1: double; c2: double c1: double; c2: double * 1 actually, the optimal value should be used together with ksl3 and ksl2. the playback speed can be varied by setting vp0 to 7 in cav-w mode. see "?. description of modes" for details. ? 91 CXD3003r ?-9. dac block playback speed the dac block playback speed is controlled by sending the dads command to the dsp block. mode 1 2 768fs 384fs 0 1 x'tal dads ?-10. dac block input timing the dac input timing chart is shown below. audio data is not transferred from the cd signal processor block to the dac block inside the CXD3003r. this is to allow data to be sent to the dac block via the audio dsp, etc. when the data is input to the dac block without using the audio dsp, the data must be connected outside the lsi. in this case, lrck, bck and pcmd can be connected directly with lrcki, bcki and pcmdi, respectively. (see the application circuit.) normal-speed playback l 1 5 i n v a l i d l 1 4 l 1 3 l 1 2 l 1 1 l 1 0 l 9 l 8 l 7 l 6 l 5 l 4 l 3 l 2 l 1 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 l 0 l r c k i ( 4 4 . 1 k ) b c k i ( 2 . 1 2 m ) p c m d i ? 92 CXD3003r ?-11. asymmetry compensation fig. 4-15 shows the block diagram and circuit example. a s y e r f a c r 1 r 1 a s y o a s y i r 1 2 r 2 5 = b i a s r 1 r 1 r 2 c x d 3 0 0 3 r 2 2 1 4 1 6 1 7 1 5 fig. 4-15. asymmetry compensation application circuit. ? 93 CXD3003r ?-12. CXD3003r clock system the dac, digital signal processor and digital servo blocks can be switched to each playback mode according to how the crystal and clock circuit are connected. each circuit is as shown in the diagram below; during normal use, fsto and fsti are directly connected to each other. 3 8 4 f s o r 7 6 8 f s x t l i x t l o o s c d a d s ( c o m m a n d r e g i s t e r ) c l o c k s u p p l i e d t o d a c 3 8 4 f s t o d a c b l o c k t o c d s i g n a l p r o c e s s o r b l o c k x t s l m c k o t o e x t e r i o r f s t o f s t i e x t e r n a l c o n n e c t i o n t o d i g i t a l s e r v o b l o c k x t 2 d x t 4 d ( c o m m a n d r e g i s t e r ) 1 / 2 1 / 2 2 / 3 1 / 2 1 / 4 x t 1 d ?94 CXD3003r [5] description of servo signal processing system functions and commands ?-1. general description of the servo signal processing system (v dd : supply voltage) focus servo sampling rate: 88.2khz (when mck = 128fs) input range: 1/4v dd to 3/4v dd output format: 7-bit pwm other: offset cancel focus bias adjustment focus search gain-down function defect countermeasure auto gain control tracking servo sampling rate: 88.2khz (when mck = 128fs) input range: 1/4v dd to 3/4v dd output format: 7-bit pwm other: offset cancel e:f balance adjustment track jump gain-up function defect countermeasure drive cancel auto gain control vibration countermeasure sled servo sampling rate: 345hz (when mck = 128fs) input range: 1/4v dd to 3/4v dd output format: 7-bit pwm other: sled move fok, mirr, dfct signal generation rf signal sampling rate: 1.4mhz (when mck = 128fs) input range: 1/4v dd to 3/4v dd other: rf zero level automatic measurement ? 95 CXD3003r ?-2. digital servo block master clock (mck) the fsti pin is the reference clock input pin. the internal master clock (mck) is generated by dividing the frequency of the signal input to fsti. the frequency division ratio is 1, 1/2 or 1/4. table 5-1 below assumes that the crystal clock generated from the digital signal processor block which is 2/3 frequency-divided of xtli is input to the fsti pin by externally connecting the fsti pin and the fsto pin. the xt4d and xt2d command can be set with d13 and d12 of $3f, and the xt1d command can be set with d1 of $3e. (default = 0) the digital servo block is designed with an mck frequency of 5.6448mhz (128fs) as typical. mode 1 2 3 4 5 6 7 384fs 384fs 384fs 768fs 768fs 768fs 768fs 256fs 256fs 256fs 512fs 512fs 512fs 512fs * * 0 * * * 1 * * 0 * * 1 0 * 1 0 * 1 0 0 1 0 0 1 0 0 0 1 1/2 1/2 1 1/2 1/4 1/4 256fs 128fs 128fs 512fs 256fs 128fs 128fs xtli fsto (fsti) xtsl xt4d xt2d xt1d frequency division ratio mck fs = 44.1khz, * : don? care table 5-1. ?-3. avrg (average) measurement and compensation the CXD3003r has a circuit that measures avrg of rfdc, vc, fe and te and a circuit that compensates these signals to control the servo effectively. avrg measurement and compensation is necessary to initialize the CXD3003r, and is able to cancel the offset. the level applied to the vc, fe, rfdc and te pins can be measured by setting d15 (vclm), d13 (flm), d11 (rflm) and d4 (tclm) of $38 respectively to 1. avrg measurement takes the level applied to each analog input pin as the average of 256 samples, and then loads each value into the avrg register. avrg measurement requires approximately 2.9ms to 5.8ms (when mck = 128fs) after the command is received. during avrg measurement, if the upper 8 bits of the command register are 38 (hex), the completion of avrg measurement operation can be confirmed through the sens pin. (see timing chart 5-2.) x l a t s e n s ( = x a v e b s y ) m a x . 1 s a v r g m e a s u r e m e n t c o m p l e t e d 2 . 9 t o 5 . 8 m s timing chart 5-2. ? 96 CXD3003r ? 97 CXD3003r ?-4. e:f balance adjustment function when the disc is rotated with the laser on, and with the fcs (focus) servo on via fcs search (focus search), the traverse waveform appears in the te signal due to disc eccentricity. in this condition, the low-frequency component can be extracted from the te signal using the built-in trk hold filter by setting d5 (tblm) of $38 to 1. the extracted low-frequency component is loaded into the trvsc register as a digital value, and the trvsc register value is established when tblm returns to 0. next, setting d2 (tlc2) of $38 to 1 compensates te and se values with the trvsc register value (subtraction), resulting the e:f balance offset to be adjusted. (see fig. 5-3.) ?-5. fcs bias (focus bias) adjustment function the fbias register value can be added to the fcs servo filter input by setting d14 (fbon) of $3a to 1. (see fig. 5-3.) when the fbias register value is set when d11 = 0 and d10 = 1 with $34f, data can be written using the 9-bit value of d9 to d1 (d9: msb). in addition, the rf jitter can be monitored by setting the soct command of $8 to 1. (see "dsp block timing chart".) the fbias register can be used as a counter by setting d13 (fbss) of $3a to 1. the fbias register functions as an up counter when d12 (fbup) of $3a = 1, and as a down counter when d12 (fbup) of $3a = 0. the number of up and down steps can be changed by setting d11 and d10 (fbv1 and fbv0) of $3a. when using the fbias register as a counter, the counter stops if the fbias value the value set beforehand in flb9 to 1 of $34 matches. also, if the upper 8 bits of the command register are $3a at this time, the counter stop can be monitored through sens. a b c f b i a s s e t t i n g v a l u e ( f b 9 t o 1 ) l i m i t v a l u e ( f l b 9 t o 1 ) s e n s p i n a : r e g i s t e r m o d e b : c o u n t e r m o d e c : c o u n t e r m o d e ( w h e n s t o p p e d ) here, assume the fbias setting value fb9 to 1 and the fbias limit value fbl9 to 1 like status a. for example, if command registers fbup = 0, fbv1 = 0, fbv0 = 0 and fbss = 1 are set from this status, down count starts from status a and approaches the set limit value. when the fbias value matches fbl9 to 1, the counter stops and the sens pin goes to high. note that the up/down counter counts at each sampling cycle of the focus servo filter. the number of steps by which the count value changes can be selected from 1, 2, 4 or 8 steps by fbv1 and fbv0. when converted to fe input, 1 step corresponds to 1/512 v dd /2. ? 98 CXD3003r t e a v r g r e g i s t e r t l c 1 t r v s c r e g i s t e r t l c 2 t o t r k i n r e g i s t e r v c a v r g r e g i s t e r t l c 0 v c l c t e f r o m a / d f e a v r g r e g i s t e r f l c 1 f b i a s r e g i s t e r f b o n t o f c s i n r e g i s t e r f l c 0 t o f z c r e g i s t e r f e f r o m a / d r f l c t o r f i n r e g i s t e r r f d c f r o m a / d r f a v r g r e g i s t e r t o s l d i n r e g i s t e r s e f r o m a / d t l c 0 t l d 0 t l c 1 t l d 1 t l c 2 t l d 2 fig. 5-3. ? 99 CXD3003r ?-6. agcntl (automatic gain control) function the agcntl function automatically adjusts the filter internal gain in order to obtain the appropriate gain with the servo loop. agcntl not only copes with the sensitivity variation of the actuator and photo diode, etc., but also obtains the optimal gain for each disc. the agcntl command is sent when each servo is turned on. during agcntl operation, if the upper 8 bits of the command register are 38 (hex), the completion of agcntl operation can be confirmed through the sens pin. (see timing chart 5-4 and "description of sens signals".) setting d9 and d8 of $38 to 1 set fcs (focus) and trk (tracking) respectively to agcntl operation. note) during agcntl operation, each servo filter gain must be normal, and the anti-shock circuit (described hereafter) must be disabled. x l a t s e n s ( = a g o k ) m a x . 1 1 . 4 s a g c n t l c o m p l e t i o n timing chart 5-4. coefficient k13 changes for agf (focus agcntl) and coefficients k23 and k07 change for agt (tracking agcntl) due to agcntl. these coefficients change from 01 to 7f (hex), and they must also be set within this range when written externally. after agcntl operation has completed, these coefficient values can be confirmed by reading them out from the sens pin with the serial readout function (described hereafter). agcntl related settings the following settings can be changed with $35, $36 and $37. fg6 to fg0; agf convergence gain setting, effective setting range: 00 to 57 (hex) tg6 to tg0; agt convergence gain setting, effective setting range: 00 to 57 (hex) ags; self-stop on/off agj; convergence completion judgment time aggf; internally generated sine wave amplitude (agf) aggt; internally generated sine wave amplitude (agt) agv1; agcntl sensitivity 1 (during rough adjustment) agv2; agcntl sensitivity 2 (during fine adjustment) aghs; rough adjustment on/off aght; fine adjustment time note) converging servo loop gain values can be changed with the fg6 to 0 and tg6 to 0 setting values. in addition, these setting values must be within the effective setting range. the default settings aim for 0 db at 1khz. however, since convergence values vary according to the characteristics of each constituent element of the servo loop, fg and tg values should be set as necessary. ? 100 CXD3003r agcntl and default operation have two stages. in the first stage, rough adjustment is performed with high sensitivity for a certain period of time (select 256/128ms with aght, when mck = 128fs), and the agcntl coefficient approaches the appropriate value. the sensitivity at this time can be selected from two types with agv1. in the second stage, the agcntl coefficient is finely adjusted to approach more appropriate value with relatively low sensitivity. the sensitivity for the second stage can be selected from two types with agv2. in the second stage of default operation, when the agcntl coefficient reaches the appropriate value and stops changing, the CXD3003r confirms that the agcntl coefficient has not changed for a certain period of time (select 63/31ms with aghj, when mck = 128fs), and then completes agcntl operation. (self-stop mode) this self-stop mode can be canceled by setting ags to 0. in addition, the first stage is omitted for agcntl operation when aghs is set to 0. an example of agcntl coefficient transitions during agcntl in various settings are shown in fig. 5-5. i n i t i a l v a l u e s e n s a g c n t l s t a r t a g c n t l c o m p l e t i o n c o n v e r g e n c e v a l u e a g c n t l c o e f f i c i e n t v a l u e s l o p e a g v 1 a g h t a g j s l o p e a g v 2 fig. 5-5. ? 101 CXD3003r ?-7. fcs servo and fcs search (focus search) the fcs servo is controlled by the 8-bit serial command $0x. (see table 5-6.) register name command d23 to d20 d19 to d16 1 0 * * 1 1 * * 0 * 0 * 0 * 1 * 0 * 1 0 0 * 1 1 focus se r vo on (focus gain normal) focus se r vo on (focus gain down) focus se r vo off, 0v out focus se r vo off, focus search voltage out focus search voltage down focus search voltage up 0 0 0 0 focus control 0 table 5-6. fcs search fcs search is required in the course of turning on the fcs servo. fig. 5-7 shows the signals for sending commands $00 ? $02 ? $03 and performing only fcs search operation. fig. 5-8 shows the signals for sending $08 (fcs on) after that. f c s d r v r f f o k f e f z c f z c c o m p a r a t o r l e v e l $ 0 0 $ 0 2 $ 0 3 0 0 f c s d r v r f f o k f e f z c $ 0 0 $ 0 2 $ 0 3 0 $ 0 8 fig. 5-7. fig. 5-8. * : don? care ? 102 CXD3003r ?-8. trk (tracking) and sld (sled) servo control the trk and sld servos are controlled by the 8-bit command $2x. (see table 5-9.) when the upper 4 bits of the command register are 2 (hex), tzc is output to the sens pin. d23 to d20 d19 to d16 0 0 * * 0 1 * * 1 0 * * 1 1 * * * * 0 0 * * 0 1 * * 1 0 * * 1 1 tracking se r vo off tracking se r vo on forward track jump reverse track jump sled se r vo off sled se r vo on forward sled move reverse sled move 0 0 1 0 tracking mode 2 table 5-9. trk servo the trk jump (track jump) level can be set with 6 bits (d13 to d8) of $36. in addition, when the trk servo is on and d17 of $1 is set to 1, the trk servo filter switches to gain-up mode. the filter also switches to gain-up mode when the lock signal goes low or when vibration is detected with the anti-shock circuit (described hereafter) enabled. CXD3003r has 2 types of filters in trk gain-up mode which can be selected by setting d16 of $1. (see table 5-17.) sld servo the sld mov (sled move) output, composed of a basic value from 6 bits (d13 to d8) of $37, is determined by multiplying this value by 1 , 2 , 3 or 4 magnification set using d17 and d16 when d18 = d19 = 0 is set with $3. (see table 5-10.) sld mov must be performed continuously for 50 s or more. in addition, if the lock input signal goes low when the sld servo is on, the sld servo turns off. note) when the lock signal is low, the trk servo switches to gain-up mode and the sld servo is turned off by the default. these operations are disabled by setting d6 (lksw) of $38 to 1. d23 to d20 d19 to d16 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 sled kick level (basic value 1) sled kick level (basic value 2) sled kick level (basic value 3) sled kick level (basic value 4) 0 0 1 1 select 3 table 5-10. * : don? care register name command register name command ? 103 CXD3003r ?-9. mirr and dfct signal generation the rf signal obtained from the rfdc pin is sampled at approximately 1.4mhz (when mck = 128fs) and loaded. the mirr and dfct signals are generated from this rf signal. mirr signal generation the loaded rf signal is applied to peak hold and bottom hold circuits. an envelope is generated from the waveforms generated in these circuits, and the mirr comparator level is generated from the average of this envelope waveform. the mirr signal is generated by comparing the waveform generated by subtracting the bottom hold value from the peak hold value with this mirr comparator level. (see fig. 5-11.) the bottom hold speed and mirror sensitivity can be selected from 4 values using d7 and 6, and d5 and 4, respectively, of $3c. r f p e a k h o l d b o t t o m h o l d p e a k h o l d b o t t o m h o l d m i r r m i r r c o m p ( m i r r o r c o m p a r a t o r l e v e l ) h l r f p e a k h o l d 1 p e a k h o l d 2 p e a k h o l d 2 p e a k h o l d 1 d f c t ( d e f e c t c o m p a r a t o r l e v e l ) h l s d f fig. 5-11. dfct signal generation the loaded rf signal is input to two peak hold circuits with different time constants, and the dfct signal is generated by comparing the difference between these two peak hold waveforms with the dfct comparator level. (see fig. 5-12.) the dfct comparator level can be selected from four values using d13 and d12 of $3b. fig. 5-12. ? 104 CXD3003r ?-10. dfct countermeasure circuit the dfct countermeasure circuit maintains the directionality of the servo so that the servo does not become easily dislocated due to scratches or defects on discs. specifically, these operations are achieved by detecting scratch and defect with the dfct signal generation circuit, and when dfct goes high, applying the low frequency element of the error signal before dfct went high to the fcs and trk servo filter inputs. (see fig. 5-13.) in addition, these operations are activated by the default. they can be disabled by setting d7 (dfsw) of $38 to 1. i n p u t r e g i s t e r h o l d r e g i s t e r h o l d f i l t e r s e r v o f i l t e r e n e r r o r s i g n a l d f c t fig. 5-13. ?-11. anti-shock circuit when vibrations occurs in the cd player, this circuit forces the trk filter to switch to gain-up mode so that the servo does not become easily dislocated. this circuit is for systems which require vibration countermeasures. concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is increased. (see fig. 5-14.) the comparator level is fixed to 1/16 of the maximum comparator input amplitude. however, the comparator level is practically variable by adjusting the value of the anti-shock filter output coefficient k35. this function can be turned on and off by d19 of $1 when the brake circuit (described hereafter) is off. (see table 5-17.) this circuit can also support an external vibration detection circuit, and can set the trk servo filter to gain-up mode by inputting high level to the atsk pin. when the upper 8 bits of the command register are $1, vibration detection can be monitored from the sens pin. t e a n t i s h o c k f i l t e r t r k g a i n u p f i l t e r t r k g a i n n o r m a l f i l t e r t r k p w m g e n a t s k s e n s c o m p a r a t o r fig. 5-14. ? 105 CXD3003r ?-12. brake circuit immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to turn on. the brake circuit prevents these phenomenon. the brake circuit is to use tracking drive as a brake by cutting unnecessary portions of it utilizing the 180 offset in the rf envelope and tracking error phase relationship which occurs when the actuator traverses the track in the radial direction from the inner track to the outer track and vice versa. (see figs. 5-15 and 5-16.) concretely, this operation is achieved by masking the tracking drive using the trkcncl signal generated by loading the mirr signal at the edge of the tzc (tracking zero cross) signal. the brake circuit can be turned on and off by d18 of $1. (see fig. 5-17.) t r k d r v f w d j m p r e v j m p s e r v o o n r f t r a c e m i r r t e 0 0 t z c e d g e t r k c n c l t r k d r v s e n s t z c o u t i n n e r t r a c k o u t e r t r a c k t r k d r v r e v j m p f w d j m p s e r v o o n r f t r a c e m i r r t e 0 0 t z c e d g e t r k c n c l t r k d r v s e n s t z c o u t o u t e r t r a c k i n n e r t r a c k fig. 5-15. fig. 5-16. d23 to d20 d19 to d16 1 0 * * 0 * * * * 1 * * * 0 * * * * 0 * * * 1 * * * * 1 * * * 0 anti shock on anti shock off brake on brake off tracking gain normal tracking gain up tracking gain up filter select 1 tracking gain up filter select 2 0 0 0 1 tracking control 1 fig. 5-17. * : don? care register name command ? 106 CXD3003r ?-13. cout signal the cout signal is output to count the number of tracks during traverse, etc. it is basically generated by loading the mirr signal at both edges of the tzc signal. and the used tzc signal can be selected among three different phases for each cout signal application. hptzc: for 1-track jumps fast phase cout signal generation with a fast phase tzc signal. (the tzc phase is advanced by a cut-off 1khz digital hpf; when mck = 128fs.) stzc: for cout signal generation when mirr is externally input and for applications other than cout generation. this is generated from sampling te at 700khz. (when mck = 128fs) dtzc: for high-speed traverse reliable cout signal generation with a delayed phase stzc signal. since it takes some time to generate the mirr signal, it is necessary to delay the tzc signal in accordance with the mirr signal delay during high-speed traverse. the cout signal output method is switched with d15 and 14 of $3. when d15 = 1 : stzc when d15 = 0 and d14 = 0 : hptzc when d15 = 0 and d14 = 1 : dtzc when the dtzc is selected, the delay can be selected from two values with d14 of $36. ?-14. serial readout circuit the following measurement and adjustment results can be read out from the sens pin by inputting the readout clock to the sclk pin by $39. (see fig. 5-18, table 5-19 and "description of sens signals".) specified commands $390c: vc avrg measurement result $3908: fe avrg measurement result $3904: te avrg measurement result $391f: rf avrg measurement result $3953: fcs agcntl coefficient result $3963: trk agcntl coefficient result $391c: trvsc adjustment result $391d: fbias register value t d l s t s p w 1 / f s c l k m s b l s b x l a t s c l k s e r i a l r e a d o u t d a t a ( s e n s ) item symbol min. typ. max. unit sclk frequency sclk pulse width delay time f sclk t spw t dls 31.3 15 16 mhz ns s table 5-19. during readout, the upper 8 bits of the command register must be 39 (hex). fig. 5-18. ? 107 CXD3003r ?-15. writing to the coefficient ram the coefficient ram can be rewritten by $34. all coefficients have default values in the built-in rom, and transfer from the rom to the ram is completed approximately 40 s (when mck = 128fs) after the xrst pin rises. (the coefficient ram cannot be rewritten during this period.) after that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address of the coefficient ram. the coefficient rewrite command is comprised of 24 bits, with d14 to d8 of $34 as the address (d15 = 0) and d7 to d0 as data. coefficient rewriting is completed 11.3 s (when mck = 128fs) after the command is received. when rewriting multiple coefficients, be sure to wait 11.3 s (when mck = 128fs) before sending the next rewrite command. ?-16. pwm output fcs, trk and sld outputs are output as pwm waveforms. in particular, fcs and trk permit accurate drive by using a double oversampling noise shaper. timing chart 5-20 and fig. 5-21 show examples of output waveforms and drive circuits. t mck = 180ns timing chart 5-20. 6 4 t m c k 6 4 t m c k 6 4 t m c k a t m c k a t m c k s f d r s r d r s l d 3 2 t m c k 3 2 t m c k 3 2 t m c k 3 2 t m c k 3 2 t m c k 3 2 t m c k f c s / t r k f f d r / t f d r f r d r / t r d r o u t p u t v a l u e + a o u t p u t v a l u e a o u t p u t v a l u e 0 t m c k a 2 t m c k a 2 t m c k a 2 t m c k a 2 m c k ( 5 . 6 4 4 8 m h z ) - - - - - - - 1 5.6448mhz ? 108 CXD3003r example of drive circuit r d r f d r 2 2 k 2 2 k 2 2 k 2 2 k d r v v c c v e e fig. 5-21. operational amplifier drive circuit ? 109 CXD3003r ?-17. dirc input pin the $2 command register can be changed by operating the dirc input pin. using the dirc pin simplifies serial data transfer during trkjmp. fig. 5-22 shows $2 command register changes produced by dirc pin changes. also, timing chart 5-23 shows dirc-based operations during trkjmp. high level must be input to the dirc pin when the xrst pin rises from low to high. q 3 0 0 1 1 q 2 0 1 0 1 s e r v o s t a t u s o f f o n f w d j m p r e v j m p q 3 1 1 1 1 q 2 1 0 1 0 s e r v o s t a t u s r e v j m p f w d j m p r e v j m p f w d j m p q 3 0 0 0 0 q 2 1 1 1 1 s e r v o s t a t u s o n o n o n o n q 1 0 0 1 1 q 0 0 1 0 1 s e r v o s t a t u s o f f o n f w d m o v r e v m o v q 1 0 0 1 1 q 0 0 1 0 1 s e r v o s t a t u s o f f o n f w d m o v r e v m o v q 1 0 0 1 1 q 0 1 1 0 1 s e r v o s t a t u s o n o n f w d m o v r e v m o v d i r c t r k s l d q 3 , q 2 , q 1 a n d q 0 c o r r e s p o n d t o d 1 9 , d 1 8 , d 1 7 a n d d 1 6 o f $ 2 . fig. 5-22. $ 2 8 l a t c h o n o f f o f f o n o n o f f o n o f f $ 2 c l a t c h x l a t d i r c f w d j u m p r e v j u m p t r k s e r v o s l d s e r v o timing chart 5-23. ? 110 CXD3003r ?-18. servo status changes produced by the lock signal when the lock signal becomes low, the trk servo switches to the gain-up mode and the sld servo turns off in order to prevent sld free-running. setting d6 (lksw) of $38 to 1 deactivates this function. in other words, neither the trk servo nor the sld servo change even when the lock signal becomes low. this enables microcomputer control. ?-19. description of commands and data sets the following description contains portions which convert internal voltages into the values when they are output externally and describe them as input conversion or output conversion. input conversion converts these voltages into the voltages entering input pins before a/d conversion. output conversion converts pwm output values into analog voltage values. ? 111 CXD3003r d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 ka6 ka5 ka4 ka3 ka2 ka1 ka0 kd7 kd6 kd5 kd4 kd3 kd2 kd1 kd0 when d15 = 0 ka6 to ka0: coefficient address kd7 to kd0: coefficient data d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 0 1 fb9 fb8 fb7 fb6 fb5 fb4 fb3 fb2 fb1 when d15 = d14 = d13 = d12 = 1 ($34f) d11 = 0, d10 = 1 fbias register write fb9 to fb1: data; fb9 is msb two's complement data. for fe input conversion, fb9 to fb1 = 011111111 corresponds to 255/256 v dd /4 and fb9 to fb1 = 100000000 to ?56/256 v dd /4 respectively. (v dd : supply voltage) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 1 0 fbl9 fbl8 fbl7 fbl6 fbl5 fbl4 fbl3 fbl2 fbl1 when d15 = d14 = d13 = d12 = d11 = 1 ($34f) d10 = 0 fbias limit register write fbl9 to fbl1: data; data compared with fb9 to 1, fbl9 = msb. when using the fbias register in counter mode, counter operation stops when the value of fb9 to 1 matches with fbl9 to 1. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 0 0 tv9 tv8 tv7 tv6 tv5 tv4 tv3 tv2 tv1 tv0 when d15 = d14 = d13 = d12 = 1 ($34f) d11 = 0, d10 = 0 trvsc register write tv9 to tv0: data; tv9 is msb two's complement data. for te input conversion, tv9 to tv0 = 0011111111 corresponds to 255/256 v dd /4 and tv9 to tv0 = 1100000000 to ?56/256 v dd /4 respectively. (v dd : supply voltage) note) when the trvsc register is read out, the data length is 9 bits. at this time, data corresponding to each bit tv8 to tv0 during external write are read out. when reading out internally measured values and then writing these values externally, set tv9 the same as tv8. $34 ? 112 CXD3003r $35 (preset: $35 58 2d) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ft1 ft0 fs5 fs4 fs3 fs2 fs1 fs0 ftz fg6 fg5 fg4 fg3 fg2 fg1 fg0 ft1, ft0, ftz: focus search-up speed default value: 010 (0.673 v dd v/s) focus drive output conversion ft1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 1.35 v dd 0.673 v dd 0.449 v dd 0.336 v dd 1.79 v dd 1.08 v dd 0.897 v dd 0.769 v dd ft0 ftz focus search speed [v/s] fs5 to fs0: focus search limit voltage default value: 011000 ( 24/64 v dd , v dd : pwm driver supply voltage) focus drive output conversion fg6 to fg0: agf convergence gain setting value default value: 0101101 $36 (preset: $36 0e 2e) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 tdzc dtzc tj5 tj4 tj3 tj2 tj1 tj0 sfjp tg6 tg5 tg4 tg3 tg2 tg1 tg0 tdzc: selects the tzc signal for generating the trkcncl signal during brake circuit operation. tdzc = 0: the edge of the hptzc or stzc signal, whichever has the faster phase, is used. tdzc = 1: the edge of the hptzc or stzc signal or the tracking drive signal zero-cross, whichever has the faster phase, is used. (see ?-12.) dtzc: dtzc delay (8.5/4.25 s, when mck = 128fs) default value: 0 (4.25 s) tj5 to tj0: track jump voltage default value: 001110 ( 14/64 v dd , v dd : pwm driver supply voltage) tracking drive output conversion sfjp: surf jump mode on/off the tracking pwm output is made by adding the tracking filter output and tjreg (tj5 to 0), by setting d7 to 1 (on) tg6 to tg0: agt convergence gain setting value default value: 0101110 * * : preset, v dd : pwm driver supply voltage ? 113 CXD3003r $37 (preset: $37 50 ba) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 fzsh fzsl sm5 sm4 sm3 sm2 sm1 sm0 ags agj aggf aggt agv1 agv2 aghs aght fzsh, fzsl: fzc (focus zero cross) slice level default value: 01 (1/8 v dd /2, v dd : supply voltage); fe input conversion fzsh 0 0 1 1 0 1 0 1 1/4 v dd /2 1/8 v dd /2 1/16 v dd /2 1/32 v dd /2 fzsl slice level sm5 to sm0: sled move voltage default value: 010000 ( 16/64 v dd , v dd : pwm driver supply voltage) sled drive output conversion ags: agcntl self-stop on/off default value: 1 (on) agj: agcntl convergence completion judgment time during low sensitivity adjustment (31/63ms, when mck = 128fs) default value: 0 (63ms) aggf: focus agcntl internally generated sine wave amplitude (small/large) default value: 1 (large) aggt: tracking agcntl internally generated sine wave amplitude (small/large) default value: 1 (large) aggf 0 (small) 1 (large) * 1/32 v dd /2 1/16 v dd /2 1/16 v dd /2 1/8 v dd /2 aggt 0 (small) 1 (large) * fe/te input conversion agv1: agcntl convergence sensitivity during high sensitivity adjustment; high/low default value: 1 (high) agv2: agcntl convergence sensitivity during low sensitivity adjustment; high/low default value: 0 (low) aghs: agcntl high sensitivity adjustment on/off default value: 1 (on) aght: agcntl high sensitivity adjustment time (128/256ms, when mck = 128fs) default value: 0 (256ms) * * : preset * : preset ? 114 CXD3003r $38 (preset: $38 00 00) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 vclm vclc flm flc0 rflm rflc agf agt dfs lksw tblm tclm flc1 tlc2 tlc1 tlc0 vclm: vc level measurement (on/off) vclc: vc level compensation for fcs in register (on/off) flm: focus zero level measurement (on/off) flc0: focus zero level compensation for fzc register (on/off) rflm: rf zero level measurement (on/off) rflc: rf zero level compensation (on/off) agf: focus auto gain adjustment (on/off) agt: tracking auto gain adjustment (on/off) dfsw: defect disable switch (on/off) setting this switch to 1 (on) disables the defect countermeasure circuit. lksw: lock switch (on/off) setting this switch to 1 (on) disables the sled free-running prevention circuit. tblm: traverse center measurement (on/off) tclm: tracking zero level measurement (on/off) flc1: focus zero level compensation for fcs in register (on/off) tlc2: traverse center compensation (on/off) tlc1: tracking zero level compensation (on/off) tlc0: vc level compensation for trk/sld in register (on/off) note) commands marked with are accepted every 2.9ms. (when mck = 128fs) all commands are on when set to 1. ? 115 CXD3003r sd6 1 0 0 1 0 data ram data for address = sd4 to sd0 coefficient ram data for address = sd5 to sd0 sd4 1 0 sd3 to sd0 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 1 * * 1 0 * * 0 1 * * 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 rf avrg register rfdc input signal fbias register trvsc register rfdc envelope (bottom) rfdc envelope (peak) rfdc envelope (peak) ?(bottom) vc avrg register fe avrg register te avrg register fe input signal te input signal se input signal vc input signal 8 bit 8 bit 9 bit 9 bit 8 bit 8 bit 8 bit 9 bit 9 bit 9 bit 8 bit 8 bit 8 bit 8 bit $399f $399e $399d $399c $3993 $3992 $3991 $398c $3988 $3984 $3983 $3982 $3981 $3980 8 bit 16 bit sd5 readout data readout data length note) coefficients k40 to k4f cannot be read out. * : don't care see the description for sro1 and sro0 of $3f concerning readout methods for the above data. d15 d14 d13 d12 d11 d10 d9 d8 dac sd6 sd5 sd4 sd3 sd2 sd1 sd0 dac: serial data readout dac mode (on/off) sd6 to sd0: serial readout data select $39 ? 116 CXD3003r $3a (preset: $3a 00 00) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 fbon fbss fbup fbv1 fbv0 0 tjd0 fps1 fps0 tps1 tps0 0 sjhd inbk mti0 fbon: fbias (focus bias) register addition (on/off) the fbias register value is added to the signal loaded into the fcs in register by fbon = 1 (on). fbss: fbias (focus bias) register/counter switching fbss = 0: register, fbss = 1: counter. fbup: fbias (focus bias) counter up/down operation switching this performs counter up/down control when fbss = 1. fbup = 0: down counter, fbup = 1: up counter. fbv1, fbv0: fbias (focus bias) counter voltage switching the number of fcs bias count-up/-down steps per cycle is decided by these bits. tjd0: this sets the tracking servo filter data ram to 0 when switched from track jump to servo on only when sfjp = 1 (during surf jump operation). fps1, fps0: gain setting when transferring data from the focus filter to the pwm block. tps1, tps0: gain setting when transferring data from the tracking filter to the pwm block. this is effective for increasing the overall gain in order to widen the servo band. operation when fps1, fps0 (tps1, tps0) = 00 is the same as usual (7-bit shift). however, 6db, 12db and 18db can be selected independently for focus and tracking by setting the relative gain to 0db when fps1, fps0 (tps1, tps0) = 00. sjhd: this holds the tracking filter output at the value when surf jump starts during surf jump. inbk: when inbk = 0 (off), the brake circuit masks the tracking drive signal with trkcncl which is generated by taking the mirr signal at the tzc edge. when inbk = 1 (on), the tracking filter input is masked instead of the drive output. mti0: the tracking filter input is masked when the mirr signal is high by setting mti0 = 1 (on). the counter changes once for each sampling cycle of the focus servo filter. when mck is 128fs, the sampling frequency is 88.2khz. when converted to fe input, 1 step is approximately 1/29 v dd /2, v dd = supply voltage. fbv1 0 0 1 1 0 1 0 1 1 2 4 8 fbv0 number of steps per cycle fps1 0 0 1 1 fps0 0 1 0 1 0db +6db +12db +18db relative gain tps1 0 0 1 1 tps0 0 1 0 1 0db +6db +12db +18db relative gain * * : preset * * : preset * ? 117 CXD3003r $3b (preset: $3b e0 50) sfox, sfo2, sfo1: fok slice level default value: 011 (28/256 v dd /2, v dd = supply voltage) rfdc input conversion sfox 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 16/256 v dd /2 20/256 v dd /2 24/256 v dd /2 28/256 v dd /2 32/256 v dd /2 40/256 v dd /2 48/256 v dd /2 56/256 v dd /2 sfo2 0 1 0 1 0 1 0 1 sfo1 slice level d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sfo2 sfo1 sdf2 sdf1 max2 max1 sfox btf d2v2 d2v1 d1v2 d1v1 rint 0 0 0 * : preset * ? 118 CXD3003r sdf2, sdf1: dfct slice level default value: 10 (0.0313 v dd v) rfdc input conversion sdf2 0 0 1 1 0 1 0 1 0.0156 v dd 0.0234 v dd 0.0313 v dd 0.0391 v dd sdf1 slice level max2, max1: dfct maximum time default value: 00 (no timer limit) max2 0 0 1 1 0 1 0 1 no timer limit 2.00ms 2.36 2.72 max1 dfct maximum time btf: bottom hold double-speed count-up mode for mirr signal generation on/off (default: off) on when set to 1. d2v2, d2v1: peak hold 2 for dfct signal generation count-down speed setting default value: 01 (0.086 v dd v/ms, 44.1khz) [v/ms] unit items indicate rfdc input conversion; [khz] unit items indicate the operating frequency of the internal counter. d1v2, d1v1: peak hold 1 for dfct signal generation count-down speed setting default value: 01 (0.688 v dd v/ms, 352.8khz) [v/ms] unit items indicate rfdc input conversion; [khz] unit items indicate the operating frequency of the internal counter. rint: this initializes the initial-state registers of the circuits which generate mirr, dfct and fok. d2v2 0 0 1 1 0 1 0 1 22.05 44.1 88.2 176.4 0.0431 v dd 0.0861 v dd 0.172 v dd 0.344 v dd d2v1 count-down speed [v/ms] [khz] 176.4 352.8 705.6 1411.2 0.344 v dd 0.688 v dd 1.38 v dd 2.75 v dd d1v2 0 0 1 1 0 1 0 1 d1v1 count-down speed [v/ms] [khz] * : preset, v dd : supply voltage * * : preset, v dd : supply voltage * * : preset, v dd : supply voltage * * : preset * ? 119 CXD3003r $3c (preset: $3c 00 80) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 coss cots cetz cetf cot2 cot1 mot2 0 bts1 bts0 mrc1 mrc0 0 0 0 0 coss, cots: these select the tzc signal used when generating the cout signal. preset = hptzc. stzc is the tzc generated by sampling the te signal at 700khz. (when mck = 128fs) dtzc is the delayed phase stzc. (the delay amount can be selected by d14 of $36.) hptzc is the fast phase tzc passed through a hpf with a cut-off frequency of 1khz. see ?-13. cetz: the input from the te pin normally enters the trk filter and is used to generate the tzc signal. however, the input from the ce pin can also be used. this function is for the center error servo. when cetz = 0, the tzc signal is generated by using the te input signal. when cetz = 1, the tzc signal is generated by using the ce input signal. cetf: when cetf = 0, the signal input to the te pin is input to the trk servo filter. when cetf = 1, the signal input to the ce pin is input to the trk servo filter. these commands output the tzc signal. cot2, cot1: this outputs the tzc signal from the cout pin. coss 1 0 0 0 1 stzc hptzc dtzc cots tzc * : preset, ? don't care * bts1 0 0 1 1 0 1 0 1 1 2 4 8 bts0 number of count-up steps per cycle mrc1 0 0 1 1 0 1 0 1 5.669 * 11.338 22.675 45.351 mrc0 setting time [ s] * : preset (when mck = 128fs) * mot2: the stzc signal is output from the mirr pin by setting mot2 to 1. these commands set the mirr signal generation circuit. bts1, bts0: this sets the count-up speed for the bottom hold value of the mirr generation circuit. the time per step is approximately 708 ns (when mck = 128fs). the preset value is bts1 = 1, bts0 = 0 like the cxd2586r. however, this is valid only when btf of $3b is 0. mrc1, mrc0: this sets the minimum pulse width for masking the mirr signal of the mirr generation circuit. as noted in ?-9, the mirr signal is generated by comparing the waveform obtained by subtracting the bottom hold value from the peak hold value with the mirr comparator level. strictly speaking, however, for mirr to become high, these levels must be compared continuously for a certain time. this sets that time. the preset value is mrc1 = 0, mrc0 = 0 same time as the cxd2586r. cot2 1 0 0 1 0 stzc hptzc cout cot1 cout pin output * : preset, ? don't care * ? 120 CXD3003r $3d (preset: $3d 00 00) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sfid sfsk thid thsk 0 tld2 tld1 tld0 0 0 0 0 0 0 0 0 sfid: sled servo filter input can be obtained not from sld in reg, but from m0d, which is the trk filter second-stage output. when the low frequency component of the tracking error signal obtained from the rf amplifier is attenuated, the low frequency can be amplified and input to the sld servo filter. sfsk: only during trk servo gain up2 operation, coefficient k30 is used instead of k00. normally the dc gain between the te input pin and m0d changes for trk filter gain normal and gain up2, and error occurs in the dc level at m0d. in this case, the dc level of the signal transmitted to m00 can be kept uniform by adjusting the k30 value even during the above switching. thid: trk hold filter input can be obtained not from sld in reg, but from m0d, which is the trk filter second-stage output. when signals other than the tracking error signal from the rf amplifier are input to the se input pin, the signal transmitted from the te pin can be obtained as trk hold filter input. thsk: only during trk servo gain up2 operation, coefficient k46 is used instead of k40. normally the dc gain between the te input pin and m0d changes for trk filter gain moral and gain up 2, and error occurs in the dc level at m0d. in this case, the dc level of the signal transmitted to m18 can be kept uniform by adjusting the k46 value even during the above switching. * please refer to ?5-21. filter composition, for further information on sfid, sfsk, thid and thsk commands. tld0 to 2: sld filter correction turns on and off independently of the trk filter. please refer also to $38 (tlc0 to 2) and figure 5-3. tlc0 0 1 0 1 off on off off on on tld0 vc level correction trk filter sld filter * : preset, ?: don't care * tlc1 0 1 0 1 off on off off on on tld1 tracking zero level correction trk filter sld filter * tlc2 0 1 0 1 off on off off on on tld2 traverse center correction trk filter sld filter * ? 121 CXD3003r input coefficient inversion when sfid = 1 and thid = 1 the preset coefficients for the trk filter are negative for input and positive for output. with this, the error input and servo that outputs reversed phase drive can be hypothesized. k 1 9 t r k f i l t e r k 2 2 n e g a t i v e i n p u t c o e f f i c i e n t p o s i t i v e o u t p u t c o e f f i c i e n t * t e k 0 0 s l d f i l t e r k 0 5 n e g a t i v e i n p u t c o e f f i c i e n t p o s i t i v e o u t p u t c o e f f i c i e n t s e k 4 0 t r k h o l d f i l t e r k 4 5 p o s i t i v e i n p u t c o e f f i c i e n t p o s i t i v e o u t p u t c o e f f i c i e n t t r k h o l d when sfid = 1, the trk filter negative input coefficient is applied to the sld filter, so invert the sld input coefficient (k00) code. (for example, inverting the code for coefficient k00: e0h results in 60h.) for the same reason, when thid = 1, invert the trk hold input coefficient (k40) code. k 1 9 t r k f i l t e r k 2 2 n e g a t i v e i n p u t c o e f f i c i e n t p o s i t i v e o u t p u t c o e f f i c i e n t * t e k 0 0 s l d f i l t e r k 0 5 p o s i t i v e i n p u t c o e f f i c i e n t p o s i t i v e o u t p u t c o e f f i c i e n t s e k 4 0 t r k h o l d f i l t e r k 4 5 n e g a t i v e i n p u t c o e f f i c i e n t p o s i t i v e o u t p u t c o e f f i c i e n t t r k h o l d m 0 d * for trk servo gain normal please refer also to ?5-21. filter composition. ? 122 CXD3003r $3e (preset: $3e 00 00) f1nm, f1dm: quasi double accuracy setting for fcs servo filter first-stage on when set to 1; default = 0. f1nm: gain normal f1dm: gain down t1nm, t1um: quasi double accuracy setting for trk servo filter first-stage on when set to 1; default = 0. t1nm: gain normal t1um: gain up f3nm, f3dm: quasi double accuracy setting for fcs servo filter third-stage on when set to 1; default = 0. generally, the advance amount of the phase becomes large by partially setting the fcs servo third-stage filter which is used as the phase compensation filter to double accuracy. f3nm: gain normal f3dm: gain down t3nm, t3um: quasi double accuracy setting for trk servo filter third-stage on when set to 1; default = 0. generally, the advance amount of the phase becomes large by partially setting the trk servo third-stage filter which is used as the phase compensation filter to double accuracy. t3nm: gain normal t3um: gain up note) filter first- and third-stage quasi double accuracy settings can be set individually. see "filter composition" at the end of this specification concerning quasi double accuracy. dfis: fcs hold filter input extraction node selection 0: m05 (data ram address 05); default 1: m04 (data ram address 04) tlcd: this command masks the tlc2 command set by d2 of $38 only when fok is low. on when set to 1; default = 0 lkin: when 0, the internally generated lock signal is output to the lock pin. (default) when 1, the lock signal can be input from an external source to the lock pin. coin: when 0, the internally generated cout signal is output to the cout pin. (default) when 1, the cout signal can be input from an external source to the cout pin. the mirr, dfct and fok signals can also be input from an external source. mdfi: when 0, the mirr, dfct and fok signals are generated internally. (default) when 1, the mirr, dfct and fok signals can be input from an external source through the mirr, dfct and fok pins. miri: when 0, the mirr signal is generated internally. (default) when 1, the mirr signal can be input from an external source through the mirr pin. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 f1nm f1dm f3nm f3dm t1nm t1um t3nm t3um dfis tlcd 0 lkin coin mdfi miri xt1d xt1d: the clock input from fsti can be used without being frequency-divided as the master clock for the servo block by setting d0 to 1. this command takes precedence over the xtsl pin, xt2d and xt4d. see the description of $3f for xt2d and xt4d. mdfi 0 0 1 0 1 mirr, dfct and fok are all generated internally. mirr only is input from an external source. mirr, dfct and fok are all input from an external source. miri * * : preset, ? don't care ? 123 CXD3003r $3f (preset: $3f 00 00) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 agg4 xt4d xt2d 0 drr2 drr1 drr0 0 asfg ftq lpas sro1 sro0 aghf 0 xt4d, xt2d: mck (digital servo master clock) frequency division setting this command forcibly sets the frequency division ratio to 1/4, 1/2 or 1/1 when mck is generated from the signal input to the fsti pin. see the description of $3e for xt1d. agg4: this varies the amplitude of the internally generated sine wave using the aggf and aggt commands during agc. when agg4 = 0, the default is used. when agg4 = 1, the setting is as shown in the table below. aggf (msb) 0 0 1 1 0 1 0 1 1/64 v dd /2 1/32 v dd /2 1/16 v dd /2 1/8 v dd /2 aggt (lsb) te/fe input conversion drr2 to drr0: partially clears the data ram values (0 write). the following values are cleared when set to 1 (on) respectively; default = 0 drr2: m08, m09, m0a drr1: m00, m01, m02 drr0: m00, m01, m02 only when lock = low note) set drr1 and drr0 on for 50 s or more. asfg: when vibration detection is performed during anti-shock circuit operation, fcs servo filter is forcibly set to gain normal status. on when set to 1; default = 0 lpas: built-in analog buffer low-current consumption mode this mode reduces the total analog buffer current consumption for the vc, te, se and fe input analog buffers by using a single operational amplifier. on when set to 1; default = 0 note) when using this mode, first check whether each error signal is properly a/d converted using the sro1 and sro0 commands of $3f. sro1, sro0: these commands are used to output various data externally continuously which have been specified with the $39 command. (however, d15 (dac) of $39 must be set to 1.) digital output (sock, xolt and sout) can be obtained from three specified pins by setting these commands to 1 respectively. the default is 0, 0. (no readout) the output pins for each case are shown below. sock xolt sout da13 pin da12 pin da14 pin da10 pin da09 pin da11 pin sro1 = 1 sro0 = 1 (see "description of data readout" on the following page.) aghf: this halves the frequency of the internally generated sine wave during agc. ftq: the slope of the output during focus search is a quarter of the conventional output slope. these settings are the same for both focus auto gain control and tracking auto gain control. * : preset, ? don't care * xt1d 0 1 0 0 xt2d 0 1 0 xt4d 0 1 according to xtsl 1/1 1/2 1/4 frequency division ratio * * : preset ? 124 CXD3003r description of data readout s o c k ( 5 . 6 4 4 8 m h z ) x o l t ( 8 8 . 2 k h z ) s o u t m s b l s b m s b l s b 1 6 - b i t r e g i s t e r f o r s e r i a l / p a r a l l e l c o n v e r s i o n 1 6 - b i t r e g i s t e r f o r l a t c h s o u t s o c k x o l t c l k c l k m s b l s b t o t h e 7 - s e g m e n t l e d t o t h e 7 - s e g m e n t l e d d a t a i s c o n n e c t e d t o t h e 7 - s e g m e n t l e d b y 4 - b i t s a t a t i m e . t h i s e n a b l e s h e x d i s p l a y u s i n g f o u r 7 - s e g m e n t l e d s . m s b l s b s o u t s o c k x o l t s e r i a l d a t a i n p u t c l o c k i n p u t l a t c h e n a b l e i n p u t a n a l o g o u t p u t d / a t o a n o s c i l l o s c o p e , e t c . o f f s e t a d j u s t m e n t , g a i n a d j u s t m e n t w a v e f o r m s c a n b e m o n i t o r e d w i t h a n o s c i l l o s c o p e u s i n g a s e r i a l i n p u t - t y p e d / a c o n v e r t e r a s s h o w n a b o v e . ? 125 CXD3003r ?-20. list of servo filter coefficients ? 126 CXD3003r ? 127 CXD3003r ?-21. filter composition the internal filter composition is shown below. k ** and m ** indicate coefficient ram and data ram address values respectively. fcs servo gain normal fs = 88.2khz k 0 d k 0 c k 0 e k 1 0 z 1 k 0 b z 1 k 0 9 k 0 a k 0 8 z 1 m 0 4 m 0 3 2 7 2 7 m 0 5 m 0 6 z 1 k 1 1 k 1 3 k 0 f f c s h o l d r e g 1 f c s a u t o g a i n f c s p w m 2 7 f c s s r c h m 0 7 2 1 k 0 6 a g f o n k 0 6 d f c t f c s h o l d r e g 2 f c s i n r e g s i n r o m fcs servo gain down fs = 88.2khz k 2 9 k 2 8 k 2 a k 2 c z 1 k 2 7 z 1 k 2 5 k 2 6 k 2 4 z 1 m 0 4 m 0 3 2 7 2 7 m 0 5 m 0 6 z 1 k 2 d k 1 3 k 2 b f c s h o l d r e g 1 f c s a u t o g a i n f c s p w m 2 7 f c s s r c h m 0 7 2 1 k 0 6 d f c t f c s h o l d r e g 2 f c s i n r e g note) set the msb bit of the k0b and k0d coefficients to 0. note) set the msb bit of the k27 and k29 coefficients to 0. ? 128 CXD3003r trk servo gain normal fs = 88.2khz k 1 f k 1 e k 2 0 k 2 1 z 1 k 1 d z 1 k 1 b k 1 c k 1 a z 1 m 0 c m 0 b 2 7 2 7 m 0 d m 0 e z 1 k 2 2 k 2 3 t r k a u t o g a i n t r k p w m 2 7 t r k j m p m 0 f 2 1 k 1 9 a g t o n k 1 9 d f c t t r k h o l d r e g t r k i n r e g s i n r o m t o s l d s e r v o , t r k h o l d note) set the msb bit of the k1d and k1f coefficients to 0. trk servo gain up 1 fs = 88.2khz k 3 d z 1 z 1 k 1 b k 3 c k 1 a z 1 m 0 c m 0 b m 0 e k 3 e k 2 3 t r k a u t o g a i n t r k p w m 2 7 t r k j m p m 0 f 2 1 k 1 9 d f c t t r k h o l d r e g t r k i n r e g ? 129 CXD3003r trk servo gain up 2 fs = 88.2khz k 3 b k 3 a k 3 c k 3 d z 1 k 3 9 z 1 k 3 7 k 3 8 k 3 6 z 1 m 0 c m 0 b 2 7 2 7 m 0 e z 1 k 3 e k 2 3 t r k a u t o g a i n t r k p w m 2 7 t r k j m p m 0 f 2 1 k 1 9 d f c t t r k h o l d r e g t r k i n r e g t o s l d s e r v o , t r k h o l d note) set the msb bit of the k39 and k3b coefficients to 0. sld servo fs = 345hz k 0 4 k 0 3 z 1 k 0 2 z 1 k 0 1 k 0 0 m 0 0 2 7 2 7 m 0 1 k 0 5 k 0 7 t r k a u t o g a i n s l d p w m 2 7 s l d m o v m 0 2 s l d i n r e g 2 1 k 3 0 s f s k ( o n l y w h e n t g u p 2 i s u s e d ) s f i d m 0 d t r k s e r v o f i l t e r s e c o n d - s t a g e o u t p u t note) set the msb bit of the k02 and k04 coefficients to 0. hptzc/auto gain fs = 88.2khz k 1 5 k 1 7 z 1 k 1 4 m 0 8 m 0 9 m 0 a z 1 a u t o g a i n r e g 2 1 a g t o n a g f o n a g f o n f c s i n r e g t r k i n r e g s i n r o m z 1 s l i c e t z c r e g s l i c e 2 1 ? 130 CXD3003r anti shock fs = 88.2khz k 3 4 k 3 3 z 1 z 1 k 3 1 k 1 6 z 1 m 0 9 m 0 8 2 7 m 0 a k 3 5 c o m p k 1 2 a n t i s h o c k r e g 2 1 t r k i n r e g note) set the msb bit of the k34 coefficient to 0. the comparator input is 1/16 the maximum amplitude of the comparator input. avrg fs = 88.2khz m 0 8 a v r g r e g 2 1 v c , t e , f e , r f d c z 1 2 7 trk hold fs = 345hz k 4 4 k 4 3 z 1 k 4 2 z 1 k 4 1 k 4 0 m 1 8 2 7 2 7 m 1 9 k 4 5 t r k h o l d r e g s l d i n r e g 2 1 k 4 6 t h s k ( o n l y w h e n t g u p 2 i s u s e d ) t h i d m 0 d t r k s e r v o f i l t e r s e c o n d - s t a g e o u t p u t note) set the msb bit of the k42 and k44 coefficients to 0. fcs hold fs = 345hz k 4 c k 4 b z 1 k 4 a z 1 k 4 9 k 4 8 m 1 0 2 7 2 7 m 1 1 k 4 d f c s h o l d r e g 1 f c s h o l d r e g 2 note) set the msb bit of the k4a and k4c coefficients to 0. ? 131 CXD3003r fcs servo gain normal; fs = 88.2khz, during quasi double accuracy (ex.: $3eaxx0) k 0 d k 0 c 8 0 h k 1 0 z 1 k 0 b z 1 7 f h k 0 a 8 1 h z 1 m 0 4 m 0 3 2 7 2 7 m 0 5 m 0 6 z 1 k 1 1 k 1 3 k 0 f f c s h o l d r e g 1 f c s a u t o g a i n f c s p w m 2 7 f c s s r c h m 0 7 2 1 k 0 6 a g f o n k 0 6 d f c t f c s h o l d r e g 2 f c s i n r e g s i n r o m k 0 8 k 0 9 2 7 2 7 k 0 e 2 7 * * * * 81h, 7fh and 80h are each hex display 8-bit fixed values when set to quasi double accuracy. note) set the msb bit of the k0b and k0d coefficients during normal operation, and of the k08, k09 and k0e coefficients during quasi double accuracy to 0. fcs servo gain down; fs = 88.2khz, during quasi double accuracy (ex.: $3e5xx0) k 2 9 k 2 8 8 0 h k 2 c z 1 k 2 7 z 1 7 f h k 2 6 8 1 h z 1 m 0 4 m 0 3 2 7 2 7 m 0 5 m 0 6 z 1 k 2 d k 1 3 k 2 b f c s h o l d r e g 1 f c s a u t o g a i n f c s p w m 2 7 f c s s r c h m 0 7 2 1 k 0 6 d f c t f c s h o l d r e g 2 f c s i n r e g k 2 4 k 2 5 2 7 2 7 k 2 a 2 7 * * * * 81h, 7fh and 80h are each hex display 8-bit fixed values when set to quasi double accuracy. note) set the msb bit of the k27 and k29 coefficients during normal operation, and of the k24, k25 and k2a coefficients during quasi double accuracy to 0. ? 132 CXD3003r trk servo gain normal; fs = 88.2khz, during quasi double accuracy (ex.: $3exax0) k 1 f k 1 e 8 0 h k 2 1 z 1 k 1 d z 1 7 f h k 1 c 8 1 h z 1 m 0 c m 0 b 2 7 2 7 m 0 d m 0 e z 1 k 2 2 k 2 3 t r k a u t o g a i n t r k p w m 2 7 t r k j m p m 0 f 2 1 k 1 9 a g t o n k 1 9 d f c t t r k h o l d r e g t r k i n r e g s i n r o m k 1 a k 1 b 2 7 2 7 k 2 0 2 7 * * * * 81h, 7fh and 80h are each hex display 8-bit fixed values when set to quasi double accuracy. note) set the msb bit of the k1d and k1f coefficients during normal operation, and of the k1a, k1b and k20 coefficients during quasi double accuracy to 0. trk servo gain up 1; fs = 88.2khz, during quasi double accuracy (ex.: $3ex5x0) k 3 d z 1 k 3 c z 1 7 f h 8 0 h 8 1 h z 1 m 0 c m 0 b 2 7 m 0 e k 3 e k 2 3 t r k a u t o g a i n t r k p w m 2 7 t r k j m p m 0 f 2 1 k 1 9 d f c t t r k h o l d r e g t r k i n r e g k 1 a k 1 b 2 7 2 7 * * * * 81h, 7fh and 80h are each hex display 8-bit fixed values when set to quasi double accuracy. note) set the msb bit of the k1a, k1b and k3c coefficients during quasi double accuracy to 0. ? 133 CXD3003r trk servo gain up 2; fs = 88.2khz, during quasi double accuracy (ex.: $3ex5x0) k 3 b k 3 a 8 0 h k 3 d z 1 k 3 9 z 1 7 f h k 3 8 8 1 h z 1 m 0 c m 0 b 2 7 2 7 m 0 d m 0 e z 1 k 3 e k 2 3 t r k a u t o g a i n t r k p w m 2 7 t r k j m p m 0 f 2 1 k 1 9 d f c t t r k h o l d r e g t r k i n r e g k 3 6 k 3 7 2 7 2 7 k 3 c 2 7 * * * * 81h, 7fh and 80h are each hex display 8-bit fixed values when set to quasi double accuracy. note) set the msb bit of the k39 and k3b coefficients during normal operation, and of the k36, k37 and k3c coefficients during quasi double accuracy to 0. ? 134 CXD3003r ?-22. tracking and focus frequency response f f r e q u e n c y [ h z ] 2 0 k 1 k 1 0 0 1 0 2 . 1 1 0 0 1 0 2 0 3 0 4 0 g g a i n [ d b ] 1 8 0 f p h a s e [ d e g r e e ] 0 1 8 0 9 0 9 0 f o c u s f r e q u e n c y r e s p o n s e n o r m a l g a i n d o w n f g f f r e q u e n c y [ h z ] 2 0 k 1 k 1 0 0 1 0 2 . 1 1 0 0 1 0 2 0 3 0 4 0 g g a i n [ d b ] 1 8 0 f p h a s e [ d e g r e e ] 0 1 8 0 9 0 9 0 t r a c k i n g f r e q u e n c y r e s p o n s e n o r m a l g a i n u p f g ? 135 CXD3003r x p l c k x u g f g t o p x o l t s o c k s o u t w d c k v c p d o a d i o g n d s p d l s l e d s s t p + 5 v d r i v e r c i r c u i t m i r r c o u t f s t o n c f s t i m c k o x t s l d v s s 2 d a 0 1 d a 0 2 d a 0 4 d a 0 5 d a 0 6 d v d d 2 d a 0 7 d a 0 8 d a 0 9 d a 1 0 n c n c s q c k s q s o e x c k s b s o s c o r w f c k m u t e d o u t m d 2 d v d d 3 c 1 6 m c 4 m n c d t s 2 x r s t s c s y n c d a 0 3 n c n c d f c t m i r r c o u t d v s s 4 x l a t d a t a x w o a t s k s c l k d i r c s e n s d v d d 4 a v d d 3 a o 1 r a v s s 3 a v s s 5 x t l i x t l o a v d d 5 a v d d 4 a o 2 f a o 2 r d v s s 3 d a s 1 d a s 0 d t s 0 d t s 1 n c f o k c l o k a o 1 f n c a v s s 4 n c p w m i f s w m o n m d p m d s l o c k s s t p d v s s 5 s f d r s r d r t f d r t r d r f f d r f r d r d v d d 5 n c v c o o v c o i t e s t t e s 2 t e s 3 p d o v c k i v 1 6 m a v d d 2 i g e n a v s s 2 a d i o r f d c c e t e n c n c t e s t a n c n c n c n c s e v p c o 2 v c t l f i l o f i l i p c o c l t v a v s s 1 r f a c b i a s a s y i a s y o a v d d 1 n c d v d d 1 d v s s 1 a s y e p s s l w d c k l r c k l r c k i d a 1 6 p c m d i d a 1 5 d a 1 4 d a 1 3 d a 1 2 d a 1 1 n c n c v c v p c o 1 f e b c k i d f c t l p f c i r c u i t l p f c i r c u i t x r a o f c 2 p o r f c k m n t 0 m n t 1 m n t 2 m n t 3 g n d m c k o c 4 m c 1 6 m d o u t w f c k s b s o e x c k f s w m o n m d s l o c k p w m i s c l k m u t e s c o r s q c k s q s o g f s c l o k x l a t d a t a x r s t s e n s f o k l d o n g n d v d d x w o s c s y g n d v c c l d o n f d t g t d f g v c t e f e f z c r f o c e 9 7 9 6 9 5 9 4 9 1 9 2 9 3 1 0 0 9 9 9 8 1 0 1 1 0 2 1 0 3 1 0 4 1 0 5 1 0 6 1 0 7 1 0 8 7 3 7 4 8 1 8 2 8 3 8 4 7 5 7 6 7 7 7 8 8 8 8 7 8 6 8 5 7 9 8 0 8 9 9 0 1 1 1 1 0 9 1 1 0 1 1 2 1 1 3 1 1 4 1 1 5 1 1 6 1 1 7 1 1 8 1 1 9 1 2 0 1 2 1 1 2 2 1 2 3 1 2 4 1 2 5 1 2 6 1 2 7 1 2 8 1 2 9 1 3 0 1 3 1 1 3 2 1 3 3 1 3 4 1 3 5 1 3 6 1 3 7 1 3 8 1 3 9 1 4 0 1 4 1 1 4 2 1 4 3 1 4 4 4 0 3 9 3 8 3 7 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 6 0 7 0 6 9 6 8 6 7 6 3 6 4 6 5 6 6 6 1 6 2 7 1 7 2 5 9 3 6 3 5 3 4 3 1 3 2 3 3 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 1 d r i v e r c i r c u i t [6] application circuit application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. ? 136 CXD3003r s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e w e i g h t e p o x y r e s i n s o l d e r p l a t i n g c o p p e r / 4 2 a l l o y l q f p - 1 4 4 p - l 0 1 l q f p 1 4 4 - p - 2 0 2 0 - a 1 . 3 g 1 4 4 p i n l q f p ( p l a s t i c ) 0 m i n ( 2 1 . 0 ) 0 . 5 0 . 1 5 0 t o 1 0 ( 0 . 1 2 5 ) 0 . 1 4 5 0 . 0 5 0 . 2 2 0 . 0 5 ( 0 . 2 ) d e t a i l a d e t a i l b 1 3 6 3 7 7 2 7 3 1 0 8 1 0 9 1 4 4 0 . 2 2 0 . 0 5 0 . 5 m 0 . 1 1 . 7 m a x a b 0 . 1 s s 2 2 . 0 0 . 2 2 0 . 0 0 . 1 s s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g c o p p e r a l l o y p a c k a g e s t r u c t u r e l q f p - 1 4 4 p - l 0 2 1 l q f p 1 4 4 - p - 2 0 2 0 1 . 3 g 1 4 4 p i n l q f p ( p l a s t i c ) 2 2 . 0 0 . 2 0 . 5 0 . 2 2 0 . 0 5 1 . 7 m a x 2 0 . 0 0 . 1 1 0 8 7 3 1 0 9 7 2 1 4 4 1 3 6 3 7 a d e t a i l a d e t a i l b ( 0 . 2 ) 0 . 2 2 0 . 0 5 ( 0 . 1 2 5 ) 0 . 1 4 5 0 . 0 5 b m 0 . 1 s 0 . 1 s s 0 t o 1 0 0 . 5 0 . 1 5 ( 2 1 . 0 ) 0 . 1 0 . 0 5 package outline unit: mm ? 137 CXD3003r package outline unit: mm s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 / c o p p e r a l l o y p a c k a g e s t r u c t u r e l q f p - 1 4 4 p - l 0 2 2 l q f p 1 4 4 - p - 2 0 2 0 1 . 3 g 1 4 4 p i n l q f p ( p l a s t i c ) 2 2 . 0 0 . 2 0 . 5 0 . 2 2 0 . 0 5 1 . 7 m a x 2 0 . 0 0 . 1 1 0 8 7 3 1 0 9 7 2 1 4 4 1 3 6 3 7 a d e t a i l a 0 t o 1 0 0 . 5 0 . 1 5 d e t a i l b ( 0 . 2 ) 0 . 2 2 0 . 0 5 ( 0 . 1 2 5 ) 0 . 1 4 5 0 . 0 5 b m 0 . 1 s 0 . 1 s s ( 2 1 . 0 ) 0 . 1 0 . 0 5 s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g c o p p e r a l l o y p a c k a g e s t r u c t u r e l q f p - 1 4 4 p - l 0 5 1 l q f p 1 4 4 - p - 2 0 2 0 1 . 3 g 1 4 4 p i n l q f p ( p l a s t i c ) d e t a i l a d e t a i l b m 0 . 0 8 0 . 1 0 t o 1 0 0 . 5 0 . 1 5 ( 2 1 . 0 ) 0 . 1 0 . 0 5 ( 0 . 2 ) 0 . 2 2 0 . 0 5 ( 0 . 1 5 ) 0 . 1 5 0 . 0 5 3 6 3 7 0 . 2 2 0 . 0 5 0 . 5 1 1 4 4 1 0 9 1 0 8 2 0 . 0 0 . 1 2 2 . 0 0 . 2 7 3 7 2 a b 1 . 7 m a x 1 . 4 0 . 1 |
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